NVIDIA Jetson Nano DG-09502-001_v2.1 | 57
Chapter 11. Miscellaneous Interfaces
11.1 I2C
Jetson Nano brings four I2C interfaces to the connector pins. CAM_I2C is included in Table
8-2. The assignments in the I2C interface mapping table should be used where applicable for
the I2C interfaces.
Table 11-1. Jetson Nano I2C Pin Description
Pin # Module Pin Name Tegra X1 Signal Usage/Description
Usage on NVIDIA DevKit
Carrier Board
Direction Pin Type
Code
Power-on
Reset
185 I2C0_SCL GEN1_I2C_SCL
General I2C 0 Clock. 2.2kΩ pull-up to 3.3V on
module.
I2C (general) Bidir
Open Drain – 3.3V
DD z
187 I2C0_SDA GEN1_I2C_SDA
General I2C 0 Data. 2.2kΩ pull-up to 3.3V on
the module.
Open Drain – 3.3V
DD z
189 I2C1_SCL GEN2_I2C_SCL
General I2C 1 Clock. 2.2kΩ pull-up to 3.3V on
the module.
Open Drain – 3.3V
DD z
191 I2C1_SDA GEN2_I2C_SDA
General I2C 1 Data. 2.2kΩ pull-up to 3.3V on
the module.
Open Drain – 3.3V
DD z
232 I2C2_SCL GEN3_I2C_SCL
General I2C 2 Clock. 2.2kΩ pull-up to 1.8V on
the module.
Open Drain – 1.8V
DD z
234 I2C2_SDA GEN3_I2C_SDA
General I2C 2 Data. 2.2kΩ pull-up to 1.8V on
the module.
Open Drain – 1.8V
DD z
Notes:
1. In the Type/Dir column, Output is from Jetson Nano. Input is to Jetson Nano. Bidir is for Bidirectional signals.
2. The MPIO Pad Codes are described in the
Tegra X1 SoC Technical Reference Manual
“Multi-Purpose I/O Pins and Pin Multiplexing
(PinMux)” section for details.
3. The Power-on Reset State column indicates the pin state when reset is active and when it is deactivated before any changes are made by
software. “z” is tristate, pu/pd indicates internal weak pull-up/down resistor is enabled, 1/0 indicates actively driven high/low.
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