NVIDIA Jetson Nano DG-09502-001_v2.1 | viii
Table 10-1. Jetson Nano Audio Pin Description.............................................................. 54
Table 10-2. Interface Signal Routing Requirements ....................................................... 56
Table 10-3. Audio Signal Connections............................................................................ 56
Table 11-1. Jetson Nano I2C Pin Description ................................................................. 57
Table 11-2. I2C Interface Signal Routing Requirements.................................................. 59
Table 11-3. I2C Signal Connections ............................................................................... 59
Table 11-4. Jetson Nano SPI Pin Description ................................................................. 59
Table 11-5. SPI Interface Signal Routing Requirements ................................................. 61
Table 11-6. Jetson Nano UART Pin Description.............................................................. 62
Table 11-7. UART Signal Connections............................................................................ 63
Table 11-8. Jetson Nano Fan Pin Description................................................................. 63
Table 11-9. Jetson Nano JTAG and Debug UART Description.......................................... 64
Table 11-10. JTAG Connections....................................................................................... 66
Table 11-11. Debug UART Connections ........................................................................... 66
Table 12-1. Pins Pulled and Driven High by Tegra Prior to SYS_RESET* Inactive ............. 68
Table 12-2. Pins Pulled High on Module with External Resistors Prior to SYS_RESET_IN*
Inactive....................................................................................................... 68
Table 13-1. Unused MPIO Pins and Pin Groups .............................................................. 69
Table 15-1. Signal Type Codes....................................................................................... 71
Table 15-2. Common High-Speed Interface Requirements ............................................. 74