Omron C200H-MC221 - Page 252

Appendix AControl Bit/Flag Timing Charts
232
23. Cycle Start Bit, Pause Bit, M Code Reset Bit, and M Code Output
Pause Bit
Operation
M Code Reset Bit
Cycle Start Bit
M Code
10
The program is paused when the Pause Bit is turned ON, but the M code isn’t cleared. M code M10 isn’t cleared by
the M Code Reset Bit because program execution is paused.
24. Cycle Start Bit, Pause Bit, M Code Reset Bit, and M Code Output
Pause Bit
Operation
M Code Reset Bit
Cycle Start Bit
M Code
100
If the Pause Bit and M Code Reset Bit are turned ON at the same time, the Pause Bit becomes valid. Program
execution is paused, but the M code isn’t cleared. When the program is restarted, the M code will be output
because it was ON originally.
25. Cycle Start Bit, Forced Block End Bit, and M Code Output
Forced Block End Bit
Operation
Cycle Start Bit
M Code
The Forced Block End Bit is turned ON while the Unit is standing by for an M code reset, cancelling the block.