RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1384
Dec 10, 2015
(3) Channel Halt Mode
In channel halt mode, settings for test-related registers of channels are performed. When a channel transitions to
channel halt mode, CAN communication of the channel stops.
Table 18-8 shows operation when the CHMDC[1:0] bits are set to B'10 (channel halt mode) during CAN
communication.
Table 18-8. Operation when a Channel Transitions to Channel Reset Mode/Channel Halt Mode
Mode During Reception During Transmission Bus Off State
Channel reset
(CHMDC[1:0] = B'01)
Transitions to channel reset
mode before reception is
completed.
Note 1
Transitions to channel reset
mode before transmission is
completed.
Note 1
Transitions to channel reset mode before
bus off recovery.
Channel halt
Note 3
(CHMDC[1:0] = B'10)
Transitions to channel halt
mode after reception is
completed.
Note 2
Transitions to channel halt
mode after transmission is
completed.
Note 2
[When BOM[1:0] = B'00]
Transitions to channel halt mode
(CHMDC[1:0] = B'10) only after bus off
recovery.
[When BOM[1:0] = B'01]
Transitions to channel halt mode
automatically when the condition for
transition to bus off state is met.
[When BOM[1:0] = B'10]
Transitions to channel halt mode
automatically after bus off recovery.
[When BOM[1:0] = B'11]
Transitions to channel halt mode
immediately after the CHMDC[1:0] bits
are set to B'10 before bus off recovery.
Notes 1. To allow transition to channel reset mode after communication is completed, set the CHMDC[1:0] bits to B'10
and confirm that communication has been completed and transition to channel halt mode has been made, and
then set the CHMDC[1:0] bits to B'01.
2. While the CAN bus is locked at the dominant level, transition to channel halt mode is not made. In that case,
enter channel reset mode. The CAN bus status can be confirmed with the BLF flag of the CiERFLL register
that becomes 1 when dominant lock is detected.
3. In case of a transition from channel reset mode to channel halt mode, transition to channel halt mode after
setting the CiCFGL and CiCFGH registers in channel reset mode.
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