RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1385
Dec 10, 2015
(4) Channel Communication Mode
In channel communication mode, CAN communication is performed. Each channel has the following communication
states during CAN communication.
• Idle : Neither reception nor transmission is in progress.
• Reception : Receiving a message sent from another node.
• Transmission : Transmitting a message.
• Bus off : Isolated from CAN communication.
When the CHMDC[1:0] bits in the CiCTRL register are set to B'00, the channel transitions to channel communication
mode. After that, when 11 consecutive recessive bits have been detected, the COMSTS flag in the CiSTSL register is set
to 1 (communication is ready) and transmission and reception are enabled on the CAN network as an active node. At this
time, transmission and reception of messages can be started.
(5) Bus Off State
A channel transitions to the bus off state according to the transmit/receive error counter increment/decrement rules of
the CAN specifications.
How to return from the bus off state is set by the BOM[1:0] bits in the CiCTRH register.
• When BOM[1:0] = B'00:
Bus off recovery is compliant with the CAN specifications. After 11 consecutive recessive bits have been
detected 128 times, a channel returns from the bus off state to the CAN communication ready state (error active
state). At that time, the TEC[7:0] and REC[7:0] bits in the CiSTSH register are initialized to H'00 and the BORF
flag in the CiERFLL register is set to 1 (bus off recovery is detected). When the CHMDC[1:0] bits in the CiCTRL
register are set to B'10 (channel halt mode) in the bus off state, the channel transitions to channel halt mode
after bus off recovery has been completed (11 consecutive recessive bits have been detected 128 times).
• When BOM[1:0] = B'01:
When a channel transitions to the bus off state, the CHMDC[1:0] bits are set to B'10 and the channel transitions
to channel halt mode. At that time, the TEC[7:0] and REC[7:0] bits are initialized to H'00 but the BORF flag is
not set to 1.
• When BOM[1:0] = B'10:
When a channel has transitioned to the bus off state, the CHMDC[1:0] bits are set to B'10. After bus off recovery
has been completed (11 consecutive recessive bits have been detected 128 times), the channel transitions to
channel halt mode. At that time, the TEC[7:0] and REC[7:0] bits are initialized to H'00 and the BORF flag is set
to 1.
• When BOM[1:0] = B'11:
When the CHMDC[1:0] bits are set to B'10 in the bus off state, the channel transitions to channel halt mode
before bus off recovery is completed. At that time, the TEC[7:0] and REC[7:0] bits are initialized to H'00 but the
BORF flag is not set to 1.
However, the BORF flag becomes 1 if a CAN module transitions to error active state (by detecting 128 times of
11 consecutive recessive bits) before CHMDC[1:0] bits are set to B'10.
If the channel transitions to channel halt mode simultaneously when the program writes a value to the CHMDC[1:0] bits,
writing by the program takes precedence. An automatic transition to channel halt mode when the BOM[1:0] bits are set to
B'01 or B'10 is made only when the CHMDC[1:0] bits are B'00 (channel communication mode). Furthermore, setting the
RTBO bit in the CiCTRL register to 1 allows forcible return from the bus off state. As soon as the RTBO bit is set to 1, the
state changes to the error active state. After 11 consecutive recessive bits have been detected, the condition of CAN
module becomes ready for communication. In this case, the BORF flag is not set to 1 and the TEC[7:0] and REC[7:0] bits
are initialized to H'00. Write 1 to the RTBO bit when the BOM[1:0] value is B'00.
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