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R & S E K 8 9 5 / R & S E K 8 9 6
User Manual
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External Interfaces
A2.9 Data Line Connection (Digital IF Signal)
Female circular connector,
5>way
(FO 562.6594)
Signal designation / level
SDATA / CMOS / data, digital output
SCLK / CMOS 3.2 MHz / clock, digital output
SFRAME / CMOS 100 kHz / frame, digital output
GND
not used
Contact
1
2
3
4
5
Mating connector:
Subminiature cable plug, 5>way
(series 711)
(FO 562.6220)
5
1
IF DIGITAL
The internal frame counter is synchronized with the negative edge of a BFO reset pulse (f 10 os)
at contact X66.20 (input). Once synchronization is completed, the signal SCITxD (contact X66.13)
will be active for the next complete frame sequence, i.e. with the beginning of the first frame the
signal changes from low to high and after the fourth frame back to low.
Each frame sequence consists of four frames. A frame is 10 os long and is made up of two 12>bit
data words. Each data word starts with the bit with the highest value. The data at output SDATA
become valid with each negative edge of the SCLK signal.
Every other data word contains the digital IF information.
6164.0717.02_01
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