-76-
Electrical Adjustment
Grp / No. Item Function Range Initial Note
16 DLYCNT (SLOT2) SLOT2 Clock Phase [Reserved] 0 - 255 1
17 DLYCNT (SLOT2) SLOT2 Clock Phase [Reserved] 0 - 255 1
18 DLYCNT (SLOT2) SLOT2 Clock Phase [Reserved] 0 - 255 1
19 DLYCNT (SLOT2) SLOT2 Clock Phase [Reserved] 0 - 255 1
90 SW FPGA -SETTING
0 LVDS_AJY_TIM AV 0 - 7 0
1 LVDS_SJY_PHASE AV 0 - 255 135
2 RSTOFF AV 0 - 1 0
3 LVDS_AJY_TIM Slot 0 - 7
4 LVDS_AJY_PHASE Slot 0 - 255 135
5 RSTOFF Slot 0 - 1 0
100 CXA7010
0 G SIG Center 0 - 255 112
1 B SIG Center 0 - 255 112
2 R SIG Center 0 - 255 112
3 G Bright Control 0 - 255 0
4 B Bright Control 0 - 255 0
5 R Bright Control 0 - 255 0
6 G Gain Control 0 - 255 208
7 B Gain Control 0 - 255 208
8 R Gain Control 0 - 255 208
9 G VCOM Control 0 - 255 150
10 B VCOM Control 0 - 255 150
11 R VCOM Control 0 - 255 150
12 G SID Control A 0 - 255 50
13 B SID Control A 0 - 255 50
14 R SID Control A 0 - 255 50
15 G SID Control B 0 - 255 50
16 B SID Control B 0 - 255 50
17 R SID Control B 0 - 255 50
18 G SID Control C 0 - 255 176
19 B SID Control C 0 - 255 176
20 R SID Control C 0 - 255 176
21 G SID Control D 0 - 255 0
22 B SID Control D 0 - 255 0
23 R SID Control D 0 - 255 0
24 G SID Control E 0 - 255 0
25 B SID Control E 0 - 255 0
26 R SID Control E 0 - 255 0
27 G SID Control F 0 - 255 0
28 B SID Control F 0 - 255 0
29 R SID Control F 0 - 255 0
30 G SIGFRINV 0 - 1 0
31 B SIGFRINV 0 - 1 1
32 R SIGFRINV 0 - 1 1
33 G SID1FRINV 0 - 1 0
34 B SID1FRINV 0 - 1 1
35 R SID1FRINV 0 - 1 1
36 G SID2FRINV 0 - 1 0
37 B SID2FRINV 0 - 1 1
38 R SID2FRINV 0 - 1 1
101 CXD3550_TG
0 SHP_R 0 - 127 25
1 SHP_G 0 - 127 25
2 SHP_B 0 - 127 25
3 SCANM 0 - 3 2
4 FRPM 0 - 3 2
5 HST_R_PC 0 - 127 7
6 HST_G_PC 0 - 127 7
7 HST_B_PC 0 - 127 7
8 HST_R_PF 0 - 127 12
9 HST_G_PF 0 - 127 12
10 HST_B_PF 0 - 127 12
11 DCK1_R_W 0 - 255 10
12 DCK1_R_F 0 - 127 24
13 DCK2_R_W 0 - 255 10
14 DCK2_R_F 0 - 127 24