Schweitzer Engineering Laboratories SEL-749M - Page 214

10.12
SEL-749M Relay Instruction Manual Date Code 20080918
Testing and Troubleshooting
Self-Test
Exception Vector CPU error Yes Latched Vector nn
Relay Disabled
CT Board A/D
Offset Warn
Measure dc offset at each input
channel
>50 mV No Not Latched
VT Board
(power up)
Fail if ID register does not
match part number
Yes Latched Status Fail
Volt Card Fail
VT Board A/D
Offset Warn
Measure dc offset at each input
channel
>50 mV No Not Latched
VT Board A/D Fail Fail if any bits between 15 and
12 are set or if number of con-
versions not as expected
Yes Latched Status Fail
Volt Card Fail
+5 V Fail Measure +5 V power supply Yes Latched Status Fail
PS_Vdc Failure
Clock Battery Warn Check battery voltage level No Not Latched
RTC Chip Unable to communicate with
clock or fails time keeping test
No Not Latched
RTC Chip
Internal RAM
Clock chip static RAM fails No Not Latched
Mainboard FPGA
(power up)
Fail if mainboard Field Pro-
grammable Gate Array does
not accept program
Yes Latched Status Fail
FPGA Failure
Mainboard FPGA
(run time)
Fail on lack of data acquisition
interrupts
Yes Latched Status Fail
FPGA Failure
PTC Short Fail if short detected NA NA
External RTD Fail if no comm, or the exter-
nal RTD module reports open
RTDs, shorted RTDs, a power
supply failure
NA NA
Back-plane
comms diagnostics
Fail if GPSB is busy on entry
to processing interval
Yes Latched Status Fail
GPSB Failure
Table 10.8 Relay Self-Tests (Sheet 2 of 2)
Self-Test Description Limits
Protection
Disabled on
Fa i l ure
Alarm
Status
Front-Panel Message
on Failure
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