Sun Microsystems SUN BLADE 150

To Next Page

To Previous Page

x Sun Blade 150 Service Manual • June 2002

C.5.5.2 USB C–11

C.5.5.3 IEEE 1394 C–11

C.5.6 PCI to PCI Bridge ASIC C–11

C.5.7 Flash PROM C–11

C.5.8 Smart Card Interface C–12

C.5.9 NVRAM/TOD C–13

C.6 Reset Types C–13

C.7 Clocking C–13

C.7.1 Clock Generation C–13

C.7.2 OpenBoot PROM Jumpers CPU Speed Selection C–14

C.8 Power Control C–15

C.8.1 Power Switch C–15

C.8.1.1 Powering on the System C–15

C.8.1.2 Interrupting the system C–15

C.8.1.3 Forcing the System to Power-Off During Software

Hang C–16

C.8.2 Power-On and Power-Off Circuitry C–16

C.8.2.1 Power-On C–16

C.8.2.2 Power-Off C–16

C.8.3 On-Board VRM C–16

C.8.3.1 On-Board VRM requirements C–17

C.8.3.2 Power-On Beep C–17

C.8.3.3 Power-On LED Control C–17

C.8.4 Optional Secondary Hard Drive C–17

C.9 Memory Architecture C–18

C.9.1 SDRAM Address Multiplexing C–20

C.9.2 DIMMs C–21

C.9.2.1 Speed and Timing C–21

C.9.3 SDRAM DIMM Configuration C–21

Sun Microsystems SUN BLADE 150 - Page 10