DVG7 module theory of operation
DVG7 module th
eory of operation
This section
describes the basic operation of the major circuit blocks in the DVG7
module.
Bus interface
This block provides the communication between the mainframe and the module
circuit.
Address generator
This block consists of a frame delay, an MPU interface, a sequencer, an SDRAM
controller, and a blanking data generator. It interfaces the Frame Memory and
the Line M
emory and controls the output sequence of the video data in these
memories.
Frame memory
The frame memory contains a series of pointers that control the order the video
lines s
tored in Line Memory are used to produce the serial digital signals.
Line memory
The memory holds the actual sample points that define a serial digital signal.
Overlay controller
This block consists of an MPU interface and an overlay controller. It inserts data
from
the Overlay Memory into the Line Memory data stream to create circular
patterns, ID text, and logo.
Overlay memory
The memory g enerates timings to multiplex the line memory data and the overlay
dat
a used for a circle, ID text, and logo overlay.
Formatter
This block consists of an audio control packet generator, a data packet generator,
an MPU interface, and an SRAM controller. The formatter inserts embedded
a
udio data in serial digital signals.
Audio memory
The memory contains embedded audio data.
Serializer
This block converts a 10 bits parallel data to SDI signal.
Black generator (Option
BK only)
This block generates black or gray (40% gray) signal for the BLACK 1 and
BLACK 2 outputs.
9–10 TG8000 Multiformat Test Signal Generator Service Manual
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