HDVG7 module theory of operation
HDVG7 module t
heory of operation
This section
describes the basic operation of the major circuit blocks in the
HDVG7 module.
Bus interface
This block provides the communication between the mainframe and the module
circuit.
Address generator
This block consists of a frame delay, an MPU interface, a sequencer, an SDRAM
controller, and a blanking data generator. It interfaces the Frame Memory and
the Line M
emory and controls the output sequence of the video data in these
memories.
Frame memory
Frame memory contains a series of pointers that control the order the video lines
stored
in Line Memory are used to produce serial digital signals.
Line memory
Line memory holds the actual sample points which define a serial digital signal.
Overlay controller
This block consists of an MPU interface and an overlay controller. It inserts data
from
the Overlay Memory into the Line Memory data stream to create circular
patterns, ID text, and logo.
Overlay memory
The memory g enerates timings to multiplex the line memory data and the overlay
dat
a used for a circle, ID text, and logo overlay.
Formatter
This block consists of a line number and CRC generator, an audio control packet
generator, a data packet generator, an MPU interface, and an SRAM controller. It
i
nserts line n umbers and embedded audio data in the serial digital signals.
Audio memory
The memory contains embedded audio data.
Serializer
The serializer converts a 20 bits parallel data to SDI signal.
Black generator
(Option BK only)
This block generates black or gray (40% gray) signal for the BLACK 1 and
BLACK 2 outputs.
13–10 TG8000 Multiformat Test Signal Generator Service Manual
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