GPS7 module theory of operation
GPS7 module th
eory of operation
The GPS7 modu
le is a GPS and genlock synchronization module with a timecode
reader and generator. This section describes the basic operation of the major
circuit blocks in the GPS7 module. (See Figure 10-2.)
All access to the GPS7 module occurs through the address and data busses, shown
as the CPU I/O bus. The interface is a PLD on the GPS7 module, which is the
central control interface for MCU data transactions to and from the GPS7 module.
Antenna connector
The GPS7 module requires an external antenna to receive the GPS time signals
from up to 12 satellites. The antenna connector applies these signals to the GPS
Receiver board.
GPS receiver loop
TheGPSReceiverboardblockisaTrimble Resolution-T module, which can
track up to 12 satellites, and e xtract and average the time information from them.
The GPS receiver produces a pulse at the rate of 1 pulse per second (PPS) which
is compared to a locally generated pulse per second (Local 1 PPS) in the Phase
Detector block. The output from the Phase Detector contains a Quantization
Error due to the time sampling method used in the G PS receiver board. The GPS
receiver also produces a serial data stream detailing the error (which can be
up to
20 ns) that is arithmetically removed from the phase detector output (the
Quantize Correction path). This corrected phase detector output can be seen on
the module diagnostic display.
The corrected phase is first filtered in the averaging and loop control block, and
then read by software. The software then writes this to a synthesizer on the
TG8000 mainframe board to control the frequency of the mainframe master
54 MHz clock. This frequency control value can also be seen on the module
diagnostic display. The mainframe 54 MHz oscillator clocks the GPS7 Master
T
ime of Day (MTOD) counter. This completes the loop, spread over the two
boards, locking the mainframe oven and MTOD counter to the incoming GPS.
TG8000 Multiformat Test Signal Generator Service Manual 10–5