Tektronix TG8000

HDLG7 module theory of operation
HDLG7 module t
heory of operation
This section
describes the basic operation of the major circuit blocks in the
HDLG7 module.
Bus interface
This block provides the communication between the mainframe and the module
circuit.
Deserializer
This block c ontains a cable equalizer and deserializer circuit that converts the
HDTV Serial Digital Input signal to a 20-bit parallel video signal with the
recovere
d parallel clock. The circuitry also detects the presence of input signal
and identifies the format and rate of the incoming signal.
Signal processing
The Signal Processing block up-interpolates the Cb and Cr data and then
color-
space converts the incoming video signal to RGB. 4:4:4 YCbCr and RGB
signals are available at the output of this block. If XYZ is desired as the output,
thegammacorrectionisremovedfromtheRGBdataandthedataiscolor-space
converted to linear XYZ data. The linear XYZ data is then converted using the
digital cinema gamma correction factor.
Converter formatter
This block allows s election of the output sample structure, separating the video
data into the dual link format, reinsertion of EAV/SAV data to the two output
signals, and adding incoming ancillary data and embedded audio to the Link
A output video signal.
Ad
dress generator
This block consists of sample and line counters that can be frame delayed from a
frame reference pulse using the MPU interface. The counter outputs are used to
control the signal generation.
S
ignal generator engine
The Signal Generator Engine contains c i rcuitry to generate the selected test signal
and the EAV and SAV blanking data using the sample and line counts from the
Address Generator.
Generator formatter
The Generator Formatter separates the generated video into two output signals
(LinkAandLinkB).
12–2 TG8000 Multiformat Test Signal Generator Service Manual