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22.1.8 Overflow-Count Overflow ..................................................................................... 209
22.1.9 Overflow-Count Compare ..................................................................................... 209
22.1.10 Capture Input ................................................................................................. 209
22.1.11 Long Compare (CC2541 Only) ............................................................................. 209
22.2 Interrupts .................................................................................................................. 209
22.3 Event Outputs (DMA Trigger and Radio Events) .................................................................... 210
22.4 Timer Start/Stop Synchronization ...................................................................................... 210
22.4.1 General .......................................................................................................... 210
22.4.2 Timer Synchronous Stop ...................................................................................... 210
22.4.3 Timer Synchronous Start ..................................................................................... 210
22.5 Timer 2 Registers ........................................................................................................ 212
23 CC253x Radio .................................................................................................................. 219
23.1 RF Core ................................................................................................................... 220
23.1.1 Interrupts ........................................................................................................ 220
23.1.2 Interrupt Registers ............................................................................................. 220
23.2 FIFO Access .............................................................................................................. 224
23.3 DMA ....................................................................................................................... 224
23.4 Memory Map .............................................................................................................. 224
23.4.1 RXFIFO ......................................................................................................... 225
23.4.2 TXFIFO .......................................................................................................... 225
23.4.3 Frame-Filtering and Source-Matching Memory Map ...................................................... 225
23.5 Frequency and Channel Programming ................................................................................ 226
23.6 IEEE 802.15.4-2006 Modulation Format .............................................................................. 226
23.7 IEEE 802.15.4-2006 Frame Format ................................................................................... 228
23.7.1 PHY Layer ...................................................................................................... 228
23.7.2 MAC Layer ...................................................................................................... 228
23.8 Transmit Mode ........................................................................................................... 229
23.8.1 TX Control ...................................................................................................... 229
23.8.2 TX State Timing ................................................................................................ 229
23.8.3 TXFIFO Access ................................................................................................ 229
23.8.4 Retransmission ................................................................................................. 230
23.8.5 Error Conditions ................................................................................................ 230
23.8.6 TX Flow Diagram .............................................................................................. 230
23.8.7 Transmitted Frame Processing .............................................................................. 232
23.8.8 Synchronization Header ....................................................................................... 232
23.8.9 Frame-Length Field ............................................................................................ 232
23.8.10 Frame Check Sequence ..................................................................................... 232
23.8.11 Interrupts ...................................................................................................... 233
23.8.12 Clear-Channel Assessment ................................................................................. 233
23.8.13 Output Power Programming ................................................................................ 233
23.8.14 Tips and Tricks ............................................................................................... 233
23.9 Receive Mode ............................................................................................................ 233
23.9.1 RX Control ...................................................................................................... 233
23.9.2 RX State Timing ................................................................................................ 234
23.9.3 Received Frame Processing ................................................................................. 234
23.9.4 Synchronization Header and Frame-Length Fields ....................................................... 235
23.9.5 Frame Filtering ................................................................................................. 235
23.9.6 Source Address Matching .................................................................................... 238
23.9.7 Frame-Check Sequence ...................................................................................... 241
23.9.8 Acknowledgement Transmission ............................................................................ 241
23.10 RXFIFO Access .......................................................................................................... 243
23.10.1 Using the FIFO and FIFOP ................................................................................. 243
23.10.2 Error Conditions .............................................................................................. 244
8
Contents SWRU191C–April 2009–Revised January 2012
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