Xilinx Virtex-4 Configuration User Guide

100 www.xilinx.com Virtex-4 FPGA Configuration User Guide
UG071 (v1.12) June 2, 2017
Chapter 8: Readback and Configuration Verification
R
If capture functionality is needed, the CAPTURE_VIRTEX4 primitive can instantiated in
the user design (Figure 8-7, page 113). Alternatively, writing the GCAPTURE command to
the CMD register can be used (see Readback Capture). To capture the state of user
registers, the user design triggers the CAP input on this primitive, storing the current
register values in configuration memory. The register values are later read out of the device
along with all other configuration memory.
Readback Command Sequences
Virtex-4 configuration memory is read from the FDRO (Frame Data Register - Output)
configuration register and can be accessed from the JTAG and SelectMAP interfaces.
Readback is possible while the FPGA design is active or in a shutdown state, although
block RAMs cannot be accessed by the user design while they are being accessed by the
configuration logic.
Accessing Configuration Registers through the SelectMAP Interface
To read configuration memory through the SelectMAP interface, users must set the
interface for write control to send commands to the FPGA, and then switch the interface to
read control to read data from the device. Write and read control for the SelectMAP
interface is determined by the RDWR_B input: the SelectMAP data pins (D0:7) are inputs
when the interface is set for Write control (RDWR_B = 0); they are outputs when the
interface is set for Read control (RDWR_B = 1).
The CS_B signal must be deasserted (CS_B =1) before toggling the RDWR_B signal,
otherwise the user causes an abort (refer to “SelectMAP ABORT” in Chapter 2 for details).
The procedure for changing the SelectMAP interface from Write to Read Control, or vice
versa, is:
1. Deassert CS_B.
2. Toggle RDWR_B.
RDWR_B = 0: Write control
RDWR_B = 1: Read control
3. Assert CS_B.
4. This procedure is illustrated in Figure 8-1.
Figure 8-1: Changing the SelectMAP Port from Write to Read Control
CS_B
RDWR_B
DATA[0:7]
UG071_48_090704
WRITE
Byte
n Byte n Byte 0
CCLK
Byte 0
READ

Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English