Xilinx Virtex-4 Configuration User Guide

Virtex-4 FPGA Configuration User Guide www.xilinx.com 37
UG071 (v1.12) June 2, 2017
Serial Configuration Interface
R
Maximum CCLK Rate Varies Between Xilinx Device Families
Older Xilinx device families require slower CCLK rates than Virtex-4 devices. For mixed
serial daisy chains, ensure the Master device does not toggle CCLK faster than the slowest
device can tolerate.
PROM File Considerations
The PROM file for a serial daisy chain is larger than the sum of all bitstreams due to
additional configuration instructions. See “Generating PROM Files.”
Ganged Serial Configuration
More than one device can be configured simultaneously from the same bitstream using a
ganged serial configuration setup (Figure 2-10). In this arrangement, the serial
configuration pins are tied together such that each device sees the same signal transitions.
One device is typically set for Master serial mode (to drive CCLK) while the others are set
for Slave serial mode. For ganged serial configuration, all devices must be identical.
Configuration can be driven from a configuration PROM or from an external configuration
controller.
Notes relevant to Figure 2-10:
1. For ganged serial configuration, the optional DONE driver must be disabled for all
devices if one device is set for Master mode, because each device might not start up on
exactly the same CCLK cycle. An external pull-up resistor is required in this case.
2. The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor is
required.
Figure 2-10: Ganged Serial Configuration
(1)
DATA
PROGRAM
CLK
DOUTDIN
M2
M1M0
M1M0
CCLK
PROGRAM_B
DONE
DIN
M2
CCLK
PROGRAM_B
DONE
INIT_B
DOUT
INIT_B
CE
RESET/OE
ug071_15_073007
Xilinx
Serial PROM
Virtex-4
Master
Serial
Virtex-4
Slave
Serial
(2)
(8)
(8)

Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English