Xilinx Virtex-4 Configuration User Guide

Virtex-4 FPGA Configuration User Guide www.xilinx.com 113
UG071 (v1.12) June 2, 2017
Readback Capture
R
Readback Capture
The configuration memory readback command sequence is identical for both Readback
Verify and Readback Capture. However, the Capture sequence requires an additional step
to sample internal register values.
Users can sample CLB and IOB registers by instantiating the CAPTURE_VIRTEX4
primitive in their design (Figure 8-7) and asserting the CAP input on that primitive while
the design is operating. On the next rising clock edge on the CAPTURE_VIRTEX4 CLK
input, the internal GRDBK signal is asserted, storing all CLB and IOB register values into
configuration memory cells. These values can then be read out of the device along with the
IOB and CLB configuration columns by reading configuration memory through the
readback process. Register values are stored in the same memory cell that programs the
register's init state configuration, thus sending the GRESTORE command to the Virtex-4
configuration logic after the Capture sequence can cause registers to return to an
unintended state.
Alternatively, the GRDBK signal can be asserted by writing the GCAPTURE command to
the CMD register. This command asserts the GRDBK signal for two CCLK or TCK cycles,
depending on the startup clock setting.
If the CAP signal is left asserted over multiple clock cycles, the Capture cell is updated
with the new register value on each rising clock edge. To limit the capture operation to the
first rising clock edge, the user can add the ONESHOT attribute to the
CAPTURE_VIRTEX4 primitive. More information on the ONESHOT attribute can be
found in the Constraints Guide.
Once the configuration memory frames have been read out of the device, the user can pick
the captured register values out of the readback data stream. The capture bit locations are
given in the logic allocation file (design.ll) as described in Figure 8-8.
Figure 8-7: Virtex-4 Library Primitive
Table 8-7: Capture Signals
Signal Description Access
GCAPTURE
Captures the state of all slice and
IOB registers. Complement of
GRESTORE.
GCAPTURE command through
the CMD register or CAP input on
capture block, user controlled.
GRESTORE
Initializes all registers as
configured.
CMD register and
STARTUP_VIRTEX4 block.
UG071_54_081404
CAP
CLK
CAPTURE_VIRTEX4
Trigger with
external or
internal signal
Synchronize
to external or
internal clock

Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English