Xilinx Virtex-4 Configuration User Guide

32 www.xilinx.com Virtex-4 FPGA Configuration User Guide
UG071 (v1.12) June 2, 2017
Chapter 2: Configuration Interfaces
R
places its DONE pin in a high-Z state while continuing to pass configuration data and
commands to downstream devices. After all devices release their DONE pins, the common
DONE signal is either pulled High externally or driven High by the last device in the chain.
On the next rising CCLK edge, all devices move out of the Release DONE pin phase and
complete their startup sequences.
It is important that all DONE pins in a Slave serial daisy chain be connected. Only the last
device in the serial daisy chain should have the DONE driver enabled. Enabling the DONE
driver on upstream devices causes contention on the DONE signal.
Configuring a Serial Daisy Chain with a Microprocessor or CPLD
If a microprocessor or CPLD is driving configuration instead of a Xilinx serial PROM, all
devices in the serial daisy chain can be set for Slave serial configuration mode, or the lead
FPGA can be set for Master serial, as shown in Figure 2-5.
Notes relevant to Figure 2-5:
1. This schematic shows one of many possible implementations.
2. The DONE pin is by default an open-drain output requiring an external pull-up
resistor. A 330Ω pull-up resistor is recommended. For all devices except the first, the
active driver on DONE must be disabled. For the first device in the chain, the active
driver on DONE can be enabled. See “Guidelines and Design Considerations for Serial
Daisy Chains.”
3. The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor is
required.
4. The BitGen startup clock setting must be set for CCLK for serial configuration.
5. The .bit file must be reformatted into a PROM file before it can be stored on the
PROM. Refer to the “Generating PROM Files” section.
6. The CCLK net requires Thevenin parallel termination. See “Board Layout for
Configuration Clock (CCLK),” page 34.
Figure 2-5: Serial Daisy Chain Configuration from Parallel EPROM and CPLD
V
CC
Control Signal
ug071_18_073007
Virtex-4
Master
Serial
Virtex-4
Slave
Serial
CPLD
INIT_B
DOUT
CLKIN
LDC_DONE
DOUT
INIT_B
DIN
CCLK
DONE
PROGRAM_B
INIT_B
DIN
CCLK
DONE
PROGRAM_B
ADDRESS[18:0]
DATAIN
ROM_CS
ADDRESS[18:0]
DATAOUT[7:0]
CE
OE
V
CC
V
CC
Non-Xilinx
PROM (Parallel)
(6)
(6)

Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English