Xilinx Virtex-4 Configuration User Guide

48 www.xilinx.com Virtex-4 FPGA Configuration User Guide
UG071 (v1.12) June 2, 2017
Chapter 2: Configuration Interfaces
R
Non-Continuous SelectMAP Data Loading
Non-continuous data loading is used in applications where the configuration controller
cannot provide an uninterrupted stream of configuration data—for example, if the
controller pauses configuration while it fetches additional data.
Configuration can be paused in two ways: by deasserting the CS_B signal (Free-Running
CCLK method, Figure 2-17) or by halting CCLK (Controlled CCLK method, Figure 2-18).
Notes relevant to Figure 2-17:
1. RDWR_B is driven Low by the user, setting the SelectMAP data pins as inputs for
configuration. RDWR_B can be tied Low if readback is not needed. RDWR_B should
not be toggled after CS_B has been asserted, as this triggers an ABORT. (See
“SelectMAP ABORT”).
2. Device is ready for configuration after INIT_B toggles High.
3. The user asserts CS_B Low, enabling SelectMAP data bus. CS_B signal can be tied Low
if there is only one device on the SelectMAP bus. If CS_B is not tied Low, it can be
asserted at any time.
4. BUSY goes Low shortly after CS_B is asserted. If CS_B is tied Low, BUSY is driven Low
before INIT_B toggles High.
5. Byte loaded on rising CCLK edge.
6. Byte loaded on rising CCLK edge.
7. The user deasserts CS_B; byte ignored.
8. The user deasserts CS_B; byte ignored.
9. Byte loaded on rising CCLK edge.
10. Byte loaded on rising CCLK edge.
11. The user deasserts CS_B; byte ignored.
12. Byte loaded on rising CCLK edge.
13. Byte loaded on rising CCLK edge.
14. Byte loaded on rising CCLK edge.
Figure 2-17: Non-Continuous SelectMAP Data Loading with Free-Running CCLK
PROGRAM_B
INIT_B
CCLK
CS_B
RDWR_B
DATA[0:7]
ug071_26_073007
BUSY
(2)
(5) (6) (7) (8) (9) (10) (11) (12) (13) (14)
(1)
(3)
(4)
High-ZHigh-Z High-Z

Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English