Xilinx Virtex-4 - Selectmap Data Loading

Virtex-4 FPGA Configuration User Guide www.xilinx.com 45
UG071 (v1.12) June 2, 2017
SelectMAP Configuration Interface
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6. The .bit file must be reformatted into a PROM file before it can be stored on the serial
PROM. Refer to the “Generating PROM Files” section.
7. On 17V00 devices, the reset polarity is programmable. Reset should be set for active
Low when using a 17V00 device in this setup.
8. The Xilinx PROM must be set for parallel mode. This mode is not available for all
devices.
9. When configuring a Virtex-4 device in SelectMAP mode from a Xilinx configuration
PROM, the RDWR_B and CS_B signals can be tied Low (see “SelectMAP Data
Loading”).
10. The CCLK net requires Thevenin parallel termination. See “Board Layout for
Configuration Clock (CCLK),” page 34.
If one device is designated as the Master, the DONE pins of all devices must be connected
and with the active DONE drivers disabled. An external pull-up resistor is required on the
common DONE signal. Careful attention must be paid to signal integrity due to the
increased fanout of the outputs from the PROM. Signal integrity simulation is
recommended.
Readback is not possible if the CS_B signals are tied together, as all devices simultaneously
attempt to drive the SelectMAP data signals.
SelectMAP Data Loading
The SelectMAP interface allows for either continuous or non-continuous data loading.
Data loading is controlled by the CS_B, RDWR_B, CCLK, and BUSY signals.
CS_B
The Chip Select input (CS_B) enables the SelectMAP bus. When CS_B is High, the Virtex-4
device ignores the SelectMAP interface, neither registering any inputs nor driving any
outputs. SelectMAP data and BUSY are placed in a high-Z state, and RDWR_B is ignored.
♦ If CS_B = 0, the device's SelectMAP interface is enabled.
♦ If CS_B = 1, the device's SelectMAP interface is disabled.
CS_B is used for arbitrating between two or more devices on a SelectMAP bus. The active
device is selected by asserting its CS_B signal, while all other devices are deactivated by
deasserting their CS_B signals. If used, the CS_B should be actively driven until the startup
cycle completes, as signaled by the EOS.
If only one device is being configured through the SelectMAP, or if ganged SelectMAP
configuration is used, the CS_B signal can be tied to ground, as illustrated in Figure 2-12
and Figure 2-15.
In Slave Serial mode, the CS_B pin can be left unconnected or can be pulled High in a noisy
environment.
RDWR_B
RDWR_B is an input to the Virtex-4 device that controls whether the SelectMAP data pins
are inputs or outputs:
♦ If RDWR_B = 0, the data pins are inputs (writing to the FPGA).
♦ If RDWR_B = 1, the data pins are outputs (reading from the FPGA).