Xilinx Virtex-4 Configuration User Guide

Virtex-4 FPGA Configuration User Guide www.xilinx.com 39
UG071 (v1.12) June 2, 2017
SelectMAP Configuration Interface
R
PROM Files for Ganged Serial Configuration
PROM files for ganged serial configuration are identical to the PROM files used to
configure single devices. There are no special PROM file considerations.
SelectMAP Configuration Interface
The SelectMAP configuration interface (Figure 2-11) provides an 8-bit bidirectional
data-bus interface to the Virtex-4 configuration logic that can be used for both
configuration and readback. (For details, refer to Chapter 8)
CCLK is an output in Master SelectMAP mode; in Slave SelectMAP, CCLK is an input. One
or more Virtex-4 devices can be configured through the SelectMAP bus.
There are four methods of configuring an FPGA in SelectMAP mode:
• Single device Master SelectMAP
• Single device Slave SelectMAP
• Multiple device SelectMAP bus
• Multiple device ganged SelectMAP
Table 2-4 describes the SelectMAP configuration interface.
Figure 2-11: Virtex-4 SelectMAP Configuration Interface
Table 2-4: Virtex-4 SelectMAP Configuration Interface Pins
Pin Name Type
Dedicated
or Dual-
Purpose
Description
M[2:0] Input Dedicated MODE pins - determines configuration mode
CCLK
Input and
Output
Dedicated
Configuration clock source for all configuration
modes except JTAG
SelectMAP
Data
Three-State
Bidirectional
Dual
Purpose
Byte-wide (SelectMAP 8 bit) configuration and
readback data bus, clocked on rising edge of
CCLK. D0 is the most-significant bit (MSB), D7 the
least-significant bit (LSB). In SelectMAP 32 bit,
configuring the data order is straight D0 = LSB
and D31 = MSB.
(1)
BUSY
DONE
CCLK
PROGRAM_B
INIT_B
SelectMap Data
M[2:0]
CS_B
RDWR_B
ug071_21_073007

Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English