20 www.xilinx.com Virtex-4 FPGA Configuration User Guide
UG071 (v1.12) June 2, 2017
Chapter 1: Configuration Overview
Load Configuration Data Frames (Step 6)
After the synchronization word is loaded and the device ID has been checked, the
configuration data frames are loaded. This process is transparent to most users. For details,
refer to Chapter 7
Cyclic Redundancy Check (Step 7)
As the configuration data frames are loaded, the device calculates a Cyclic Redundancy
Check (CRC) value from the configuration data packets. After the configuration data
frames are loaded, the configuration bitstream can issue a Check CRC instruction to the
device, followed by an expected CRC value. If the CRC value calculated by the device does
not match the expected CRC value in the bitstream, the device pulls INIT_B Low and
aborts configuration. The CRC check is included in the configuration bitstream by default,
although the designer can disable it if desired. (Refer to the Development System Reference
Guide, BitGen section.) If the CRC check is disabled, there is a risk of loading incorrect
XC4VLX200 01734093
Notes:
1. Does not reflect the actual device array size.
Table 1-7: Signals Relating to the Device ID Check
Signal Name Type Access
(1)
Description
ID_Err Status Internal signal. Accessed
only through the Virtex-4
status register.
Indicates a mismatch between the
device ID specified in the bitstream
and the actual device ID.
Notes:
1. Information on the Virtex-4 status register is available in Table 7-9. Information on accessing the JTAG
capture sequence is available in Table 8-4.
Table 1-6: Virtex-4 Device ID Codes (Continued)
Device IDCODE Device IDCODE Device IDCODE
Figure 1-8: Load Configuration Data Frames (Step 6)
Device
Power-Up
Sample Mode
Pins
Synchronization
Device ID
Check
CRC Check
Clear
Configuration
Memory
Startup
Sequence
Load
Configuration
Data
Start
Finish
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Figure 1-9: Cyclic Redundancy Check (Step 7)
Device
Power-Up
Sample Mode
Pins
Synchronization
Device ID
Check
CRC Check
Clear
Configuration
Memory
Startup
Sequence
Load
Configuration
Data
Start
Finish
ug071_09_122105
Bitstream
Loading
Steps
12345678