Xilinx Virtex-4 Configuration User Guide

102 www.xilinx.com Virtex-4 FPGA Configuration User Guide
UG071 (v1.12) June 2, 2017
Chapter 8: Readback and Configuration Verification
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To read registers other than STAT, the address specified in the Type-1 packet header in Step
2 of Table 8-1 should be modified and the word count changed if necessary. Reading from
the FDRO register is a special case that is described in Configuration Memory Read
Procedure (SelectMAP).
Configuration Memory Read Procedure (SelectMAP)
The process for reading configuration memory from the FDRO register is similar to the
process for reading from other registers. Additional steps are needed to accommodate the
configuration logic. Configuration data coming from the FDRO register passes through the
frame buffer. The first frame of readback data should be discarded.
1. Write the Synchronization word to the device.
2. Write 1 NOOP command.
3. Write the RCRC command to the CMD register.
4. Write 2 NOOP commands.
5. Write the Shutdown command.
6. Write four NOOP instructions to ensure the shutdown sequence has completed.
DONE goes Low during the shutdown sequence.
7. Write the RCFG command to the CMD register.
8. Write the Starting Frame Address to the FAR (typically 0x00000000)
9. Write the read FDRO register packet header to the device. The FDRO read length is
given by:
FDRO Read Length = (words per frame) x (frames to read + 1) + 1
One extra frame is read to account for the frame buffer. The frame buffer produces one
dummy frame at the beginning of the read and one at the end. Also, one extra word is
read in SelectMap8 mode.
10. Write two dummy words to the device to flush the packet buffer.
11. Read the FDRO register from the SelectMAP interface. The FDRO read length is the
same as in step 8 above.
12. Write one NOOP instruction.
13. Write the START command.
14. Write the RCRC command.
15. Write the DESYNC command.
16. Write at least 64 bits of NOOP commands to flush the packet buffer. Continue sending
CCLK pulses until DONE goes High.
Each of these steps is performed by a single configuration packet except for step 1 and
step 8. Synchronization (step 1) and the large FDRO read (step 8) are performed by a
Type-1, Type-2 packet combination. Table 8-2 shows the readback command sequence.

Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English