Xilinx Virtex-4 Configuration User Guide

94 www.xilinx.com Virtex-4 FPGA Configuration User Guide
UG071 (v1.12) June 2, 2017
Chapter 7: Configuration Details
R
Configuration Options Register (COR)
The Configuration Options Register is used to set certain configuration options for the
device. The name of each bit position in the COR is given in Figure 7-3 and described in
Table 7-10.
DCI_MATCH
3
0: DCI not matched
1: DCI is matched
This is a logical AND function of all the MATCH signals (one
per bank). If no DCI I/Os are in a particular bank, the bank's
MATCH signal = 1.
DCM_LOCK
2
0: DCMs not locked
1: DCMs are locked
This is a logical AND function of all DCM LOCKED signals.
Unused DCM LOCKED signals = 1.
PART_SECURED
1
0: Decryptor security not set
1: Decryptor security set
CRC_ERROR
0
0: No CRC error
1: CRC error
Table 7-9: Status Register Description (Continued)
Name Bit Index Description
Figure 7-3: Configuration Options Register
Description
Reserved Reserved Reserved CRC_BYPASS Reserved Reserved DONE_PIPE DRIVE_DONE SINGLE OSCFSEL SSCLKSRC DONE_CYCLE MATCH_CYCLE LOCK_CYCLE GTS_CYCLE GWE_CYCLE
Bit Index
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9 8 76543 210
Value 0000000000000000xxxxxxxxxxxxxxxx
Table 7-10: Configuration Options Register Description
Name Bit Index Description
CRC_BYPASS
28
0: CRC enabled.
1: CRC disabled.
DONE_PIPE
25
0: No pipeline statue for DONEIN
1: Add pipeline stage for DONEIN
The FPGA waits on DONE that is delayed by one
StartupClk cycle. Use this option when StartupClk is
running at high speeds.
DRIVE_DONE
24
0: DONE pin is open drain
1: DONE is actively driven High

Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English