Xilinx Virtex-4 - Page 95

Virtex-4 FPGA Configuration User Guide www.xilinx.com 95
UG071 (v1.12) June 2, 2017
Configuration Control Logic
R
SINGLE
23
0: Readback is not single-shot
New captured values are loaded on each successive
CAP assertion on the CAPTURE_VIRTEX4
primitive. Capture can also be performed with the
GCAPTURE instruction in the CMD register.
1: Readback is single-shot.
The RCAP instruction must be loaded into the CMD
register between successive readbacks.
OSCFSEL
22:17
Select CCLK frequency in Master configuration
modes.
SSCLKSRC
16:15
Startup-sequence clock source.
00: CCLK
01: UserClk (per connection on the
CAPTURE_VIRTEX4 block)
1x: JTAGClk
DONE_CYCLE
14:12
Startup cycle to release the DONE pin.
001: Startup cycle 2
010: Startup cycle 3
011: Startup cycle 4
100: Startup cycle 5
101: Startup cycle 6
MATCH_CYCLE
11:9
Startup cycle to stall in until DCI matches.
000: Startup cycle 1
001: Startup cycle 2
010: Startup cycle 3
011: Startup cycle 4
100: Startup cycle 5
101: Startup cycle 6
111: No Wait
LOCK_CYCLE
8:6
Startup cycle to stall in until DCMs lock.
000: Startup cycle 1
001: Startup cycle 2
010: Startup cycle 3
011: Startup cycle 4
100: Startup cycle 5
101: Startup cycle 6
111: No Wait
Table 7-10: Configuration Options Register Description (Continued)
Name Bit Index Description