Xilinx Virtex-4 Configuration User Guide

Virtex-4 FPGA Configuration User Guide www.xilinx.com 99
UG071 (v1.12) June 2, 2017
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Chapter 8
Readback and Configuration Verification
Virtex®-4 devices allow users to read configuration memory through the SelectMAP or
JTAG interface. There are two styles of readback: Readback Verify and Readback Capture.
During Readback Verify, the user reads all configuration memory cells, including the
current values on all user memory elements (LUT RAM, SRL16, and block RAM).
Readback Capture is a superset of Readback Verify—in addition to reading all
configuration memory cells, the current state of all internal CLB and IOB registers is read,
and is useful for design debugging.
Note:
Virtex-4QV device configuration memory readback is only supported during design debug.
Xilinx does not support or recommend using configuration memory readback in flight applications.
The Correcting Single-Event Upsets in Virtex-4 FPGA Configuration Memory application note
(XAPP1088) describes the recommended solution to correct single event upsets (SEUs) for
Virtex-4QV FPGAs in flight. This application note is available on the High Reliability and Space
Developers’ Site.
To read configuration memory, users must send a sequence of commands to the device to
initiate the readback procedure; once initiated the device dumps the contents of its
configuration memory to the SelectMAP or JTAG interface. The configuration memory
read procedure sections for SelectMAP, IEEE 1149.1 JTAG, and IEEE 1532 JTAG describe
the steps for reading configuration memory
Users can send the readback command sequence from a custom microprocessor, CPLD, or
FPGA-based system, or use iMPACT to perform JTAG-based readback verify. iMPACT, the
device programming software provided with the ISE® tools, can perform all readback and
comparison functions for Virtex-4 devices and report to the user whether there were any
configuration errors. iMPACT cannot perform capture operations, although Readback
Capture is seldom used for design debugging because the Chipscope™ Integrated Logic
Analyzer (ILA), sold separately through the Xilinx website, provides superior design
debugging functionality in a user-friendly interface.
Once configuration memory has been read from the device, the next step is to determine if
there are any errors by comparing the readback bitstream to the configuration bitstream.
The “Verifying Readback Data” section explains how this is done.
Preparing a Design for Readback
There are two mandatory bitstream settings for readback: the BitGen security setting must
not prohibit readback (-g security:none), and bitstream encryption must not be used.
Additionally, if readback is to be performed through the SelectMAP interface, the port
must be set to retain its function after configuration by setting the persist option in BitGen
(-g Persist:Yes), otherwise the SelectMAP data pins revert to user I/O, precluding
further configuration operations. Beyond these security and encryption requirements, no
special considerations are necessary to enable readback through the Boundary-Scan port.

Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English