Xilinx Virtex-4 Configuration User Guide

Virtex-4 FPGA Configuration User Guide www.xilinx.com 109
UG071 (v1.12) June 2, 2017
Readback Command Sequences
R
Configuration Memory Read Procedure (1532 JTAG)
The IEEE 1532 JTAG readback procedure differs slightly from the IEEE 1149.1 JTAG
readback procedure in that readback commands are not sent to the configuration logic
through the CFG_IN JTAG register, rather the ISC_READ JTAG register is used to read
configuration memory directly.
At the end of 1532 JTAG readback, CRC Error status must be cleared by issuing Reset CRC
command or writing the correct CRC value to CRC register. The 1532 JTAG readback
procedure is illustrated in Figure 8-3.
Figure 8-3: IEEE 1532 JTAG Readback Flow
Table 8-6: Readback Files
File
Extension
File
Type
BitGen
Setting
Description
.rba ASCII
-b and -g
Readback
An ASCII file that contains readback commands, rather than
configuration commands, and expected readback data
where the configuration data normally is. This file must be
used with the .msk file
.rbb
Binary
-g
Readback
Binary version of .rba file. This file must be used with
the .msk file.
.rbd
ASCII
-g
Readback
An ASCII file that contains only expected readback data,
including the initial pad frame. No commands are included.
This file must be used with the .msd file.
START
Load ISC_ENABLE
Load ISC_DISABLE
Go to Test Logic Reset
Load ISC_READ
Load ISC_PROGRAM
Load ISC_PROGRAM
RTI minimum
12 TCK cycles
RTI minimum
12 TCK cycles
RTI
1 TCK cycle
RTI
1 TCK cycle
Load 32 bits of
bitstream data
Load Reset CRC
command
Load 5'b00000
N
Y
N
Y
A
STOP
A
Shift 37 bits of
readback data +
status
EO
Data
EO
bitstream
UG071_50_081404

Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English