Xilinx Virtex-4 - Page 108

108 www.xilinx.com Virtex-4 FPGA Configuration User Guide
UG071 (v1.12) June 2, 2017
Chapter 8: Readback and Configuration Verification
R
5
Remain in RTI for 12 TCK cycles. X 0 12
Move into the Select-IR state. X 1 2
Move into the Shift-IR State. X 0 2
6
Shift the first 9 bits of the CFG_IN instruction,
LSB first.
111000101 09
Shift the MSB of the CFG_IN instruction while
exiting SHIFT-IR.
111
Move into the SELECT-DR state. X 1 2
Move into the SHIFT-DR state. X 0 2
7
Shift configuration packets into the CFG_IN
data register, MSB first.
a: 0xFFFFFFFF
b: 0xAA995566
c: 0x20000000
d: 0x30008001
e: 0x00000004
f: 0x30002001
g: 0x00000000
h: 0x28006000
i: 0x48024090
j: 0x20000000
0x20000000
0 351
Shift the LSB of the last configuration packet
while exiting SHIFT-DR.
011
Move into the SELECT-IR State. X 1 3
Move into the SHIFT-IR State. X 0 2
8
Shift the first 9 bits of the CFG_OUT
instruction, LSB first.
111000100
(CFG_OUT)
09
Shift the MSB of the CFG_OUT instruction
while exiting Shift-IR.
111
Move into the SELECT-DR state. X 1 2
Move into the SHIFT-DR state. X 0 2
9
Shift the contents of the FDRO register out of
the CFG_OUT data register.
…0
number of
readback
bits – 1
Shift the last bit of the FDRO register out of the
CFG_OUT data register while exiting SHIFT-
DR.
X11
Move into the Select-IR state. X 1 3
Move into the Shift-IR State. X 0 2
10
End by placing the TAP controller in the TLR
state.
X15
Table 8-5: Shutdown Readback Command Sequence (JTAG) (Continued)
Step Description
Set and Hold
# of Clocks
(TCK)
TDI TMS