Virtex-4 FPGA Configuration User Guide www.xilinx.com 17
UG071 (v1.12) June 2, 2017
Setup (Steps 1-3)
Configuration memory is cleared sequentially any time the device is powered up, when
the PROGRAM_B pin is pulsed Low, or when the JTAG JPROGRAM instruction is used.
During this time, I/Os are placed in a high-Z state except for the dedicated Configuration
and JTAG pins. INIT_B is held Low by the device during initialization, then released after
T
POR
(Figure 1-3.) If the INIT_B pin is held Low externally, the device waits at this point in
the initialization process until the pin is released.
The minimum Low pulse time for PROGRAM_B is defined by the T
PROGRAM
timing
parameter. The PROGRAM_B pin can be held active (Low) for as long as necessary, and the
device remains held in the reset state.
Sample Mode Pins (Step 3)
When the INIT_B pin transitions to High, the device samples the MODE pins and begins
driving CCLK if in Master Serial or Master SelectMAP mode. At this point, the device
begins sampling the configuration data input pins (D
IN
pin for Serial Modes or the D0–D7
pins for SelectMAP modes on rising configuration clock signals).
Delaying Configuration
There are two ways to delay configuration for Virtex-4 devices:
• The first is to hold the INIT_B pin Low during initialization (Figure 1-3). This method
only works if INIT_B is prevented from going High. After INIT_B goes High,
configuration cannot be delayed by subsequently pulling INIT_B Low.
• The second is to hold the PROG pin Low, continuously clearing configuration
memory (“Clear Configuration Memory (Step 2, Initialization),” page 16). The signals
relating to initialization and delaying configuration (Table 1-4).
Figure 1-5: Sample Mode Pins (Step 3)
Device
Power-Up
Sample Mode
Pins
Synchronization
Device ID
Check
CRC Check
Clear
Configuration
Memory
Startup
Sequence
Load
Configuration
Data
Start
Finish
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