Xilinx Virtex-4 - Chapter 2: Configuration Interfaces; Serial Configuration Interface

Virtex-4 FPGA Configuration User Guide www.xilinx.com 27
UG071 (v1.12) June 2, 2017
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Chapter 2
Configuration Interfaces
Virtex®-4 devices have three configuration interfaces. Each configuration interface
corresponds to one or more configuration modes, shown in Table 2-1. For detailed
interface timing information, see the Virtex-4 FPGA Data Sheet.
Serial Configuration Interface
In serial configuration modes, the FPGA is configured by loading one configuration bit per
CCLK cycle:
• In Master serial mode, CCLK is an output.
• In Slave serial mode, CCLK is an input.
Figure 2-1 shows the basic Virtex-4 serial configuration interface.
There are four methods of configuring an FPGA in serial mode:
• Master serial configuration
• Slave serial configuration
• Serial daisy chain configuration
• Ganged serial configuration
Table 2-1: Configuration Interfaces and Corresponding Configuration Modes
Configuration Interface Corresponding Configuration Mode(s)
Serial Master Serial, Slave Serial
SelectMAP (8-bit or 32-bit) Master SelectMAP, Slave SelectMAP
JTAG JTAG