Xilinx Virtex-4 - Page 74

74 www.xilinx.com Virtex-4 FPGA Configuration User Guide
UG071 (v1.12) June 2, 2017
Chapter 3: Boundary-Scan and JTAG Configuration
R
Figure 3-10: Signal Diagram for Successful First Time ISC Configuration
Figure 3-11: Signal Diagram for Successful ISC Partial and Full Reconfiguration
IDCODE
Unprog. ISC_Accessed
Disable (3-stated)
ISC_Complete Operational
Active
Start-up
ISC_ENABLE Anything but ISC_DISABLE ISC_DISABLE BYPASSTAP Instr.
ISC_Enabled
ISC_Done
End of Startup
Modal State
System
Output
ug071_37_121703
IDCODE
Operational
ISC_Accessed
Disabled
ISC_Complete Operational
Active
Start-up
ISC_ENABLE Anything but ISC_DISABLE ISC_DISABLE BYPASS TAP Instr.
ISC_Enabled
ISC_Done
End of Startup
Modal State
System
Output
ug071_38_121703