Xilinx Virtex-4 Configuration User Guide

76 www.xilinx.com Virtex-4 FPGA Configuration User Guide
UG071 (v1.12) June 2, 2017
Chapter 4: Frame ECC Logic
R
S[11] = 1, S[10:0] = 0: single-bit error; overall parity bit p[11] is in error.
S[11]
= 0, S[10:0] ≠ 0: double-bit error, not correctable.
In case of a single-bit error in the frame data, the syndrome bits S[10:0] points to the flipped
bit in the address space from 704 (location of the first bit in the frame) to 2047 (last bit in the
frame). To convert the syndrome value S[10:0] to the index of the flipped bit in the range 0
to 1311, subtract 704 decimal (2C0 hexadecimal or 01011000000 binary) if the syndrome
is less than 1,024 decimal; otherwise, subtract 736 decimal (2E0 hexadecimal or
01011100000 binary). This is equivalent to subtracting 22 or 23 decimal from S[10:5], and
can be calculated as bit_index = {S[10:5] –6'd22-S[10],S[5:0]}.
If S[10:0] is 0 or a power of 2, however, an error in a parity bit has occurred. The Hamming
parity bits are stored in locations 640-651. If bit S[11] indicates a single-bit error, then (in the
case of a Hamming code parity bit error) a 1 is presented in the appropriate power-of-2 bit
position, with the other syndrome bits set to 0:
100000000001 -> 640
100000000010 -> 641
100000000100 -> 642
100000001000 -> 643
100000010000 -> 644
100000100000 -> 645
100001000000 -> 646
100010000000 -> 647
100100000000 -> 648
101000000000 -> 649
110000000000 -> 650
100000000000 -> 651

Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English