171
Addition operation data address
Addition operation data address
3) Suitable soft components
*Notes: D includes D, HD; TD includes TD, HTD; CD includes CD, HCD, HSCD, HSD; DM
includes DM, DHM; DS includes DS, DHS. M includes M, HM, SM; S includes S, HS; T
includes T, HT; C includes C, HC.
<32 bits operation>
EADD D10 D20 D50
S1· S2· D·
X0
<64 bits operation>
The two binary floating source data do addition operation, the result will be stored in target
address.
If a constant K or H used as source data, the value is converted to floating point before the
addition operation.
The registers in EDADD must start with an even address.
<32 bits operation>
(D11,D10) + (D21,D20) → (D51,D50)
(K1234) + (D101,D100) → (D111,D110)
Binary converts to Floating Binary Floating Binary Floating
(D13, D12,D11, D10)+ (D23, D22,D21, D20)→(D53, D52,D51, D50)
Binary Floating Binary Floating Binary Floating
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