221
*Notes: D includes D, HD; TD includes TD, HTD; CD includes CD, HCD, HSCD, HSD;
DM includes DM, DHM; DS includes DS, DHS. M includes M,HM,SM；S includes S,HS；
T includes T,HT；C includes C, HC.
When the high-speed counter HSC0 counts in AB phase mode, high-speed counting
value is compared to data block starting from HD100 (such as HD102, HD102,
HD104 and other double-word registers), it will immediately produce the
corresponding high-speed counting interrupt when the condition is met, each section
of the corresponding interrupt marks please refer to chapter 5-9-4.
During the high-speed counting process, it is invalid to modify the set value of 100
segments.
In the process of high-speed counting, the driving condition M0 can not be
disconnected. If M0 is disconnected and then rebooted, no interruption will occur.
The high-speed counter must be reset first, and thenset ON M0 again to produce
interruption.
When the interrupt is finished in a single execution, if it needs to start the interruption
again, the high-speed counter must be reset first, and then the driving condition must
be ON again.
In interrupt loop mode, interrupts can be generated in sequence as long as M0
remains on state.
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