Preliminary Technical Data UG-1828
Rev. PrC | Page 11 of 338
Table 1. Constrains and Limitations in Single-Band 2T2R FDD Type Small-Cell Application
Functionality Constrains and Limitations
Receiver Signal
Path
The user must ensure that appropriate level of isolation between Rx1 and Rx2 as well as Rx to Tx is provided at the
system level. In the previously described example, the RxB inputs are used only during initialization calibrations.
Ensure that the appropriate attenuation is present in line to prevent Rx being overloaded by Tx signal.
Transmit Signal
Path
The user must ensure that appropriate level of isolation between Tx1 and Tx2 as well as Rx to Tx is provided at the system
level.
LO Generation In FDD type Small Cell application, ADRV9001 can use its internal LO to generate RF LO1 for uplink (Rx1 and Rx2) and
RF LO2 for downlink (Tx1 and Tx2). It is also possible to use external LO inputs in this mode of operation. External LO1
operating at 2x RF LO can be used for uplink and External LO2 operating at 2x RF LO can be used for downlink.
RF Front End For LO generation, the ADRV9001 uses internal VCO that generates square wave type signal. A square wave LO would
produce harmonics. For example: depending of RF matching used on the RF ports user 2nd LO harmonic can be as
high as -50dBc and 3rd harmonic can be as high as −9 dBc. Therefore the RF filtering on the Rx and Tx path must
ensure that signals at the LO harmonic frequencies (up to 9th in some cases) are not affecting overall system
performance.
DPD The DPD functionality is not available when ADRV9001 operates in 2R2T FDD mode.
Calibrations During Rx initialization sequence user needs to ensure that there are no signals present at the Rx input (external LNA
should be disabled) and appropriate termination should be present at LNA output to avoid reflections of Rx
calibration tones. The maximum input signal amplitude must not exceed −82 dBm/MHz for wideband modes, TBD
dBm/MHz for narrowband modes. During Tx initialization sequence user needs to ensure that the power amplifier is
powered down to avoid unwanted emission of transmitter calibration tones at the antenna. No transmitter tracking
calibrations are available when ADRV9001 operates in 2R2T FDD mode.
AGPIOs Analog GPIOs (operating at 1.8 V level) can be used as read or write digital levels of in the end user system. AGPIOs
can be used to control states of external components or read back digital logic levels from external components.
DGPIOs Digital GPIOs can be used to perform real-time monitoring of states of internal ADRV9001 blocks. Digital GPIOs
operating as inputs can allow user to control Rx gain, Tx attenuation, AGC operation and other elements of ADRV9001
TRx. Depending on the ADRV9001 operation up to 4 GPIOs may be used by data port interface.
AuxADC AuxADC can be used to monitor analog voltage (for example, temperature sensor). Maximum AuxADC input voltage
must not exceed 0.9 V.
AuxDAC AuxDAC can be used to control the VCXO responsible for generating the ADRV9001 device clock and control any
circuitry that requires analog control voltage up to 1.8 V.
DEV_CLK_OUT ADRV9001 provides divided down version of DEV_CLK reference clock input signal on the DEV_CLK_OUT output. This
output is intended to provide reference clock signal to the digital components in the overall system. This output can
be configured to be active after power-up and before ADRV9001 configuration stage.
Multichip Sync If there is no need for multichip synchronization, the ADRV9001 can be initialized using API functions only.
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