UG-1828 Preliminary Technical Data
Rev. PrC | Page 124 of 338
DATAPATH
The high level datapath is shown in Figure 127, which is composed of an analog front end (AFE) and a digital front end (DFE).
Figure 127. Tx Datapath Block Diagram
In the DFE subsystem, the SSI interface passes data to the transmitter preprocessing blocks, including a symbol mapping/interpolation
and a 128-tap programmable FIR filter (PFIR). The symbol mapping/interpolation is used to perform interpolation and/or symbol
mapping necessary for certain NB standards. Please note that if it is the configured as an interpolator, proper filtering of the interpolation
images needs to be ensured in the PFIR. The PFIR is followed by 2 interpolation stages through a flexible combination of interpolation
filters. The interpolation ratios and filters are controlled by the profiles. By design, the interpolation images are rejected by more than
110dB. Between the 2 interpolation stages, there is an optional FM/FSK modulator named IQ FM/FSK and a digital upconverter (DUC)
which could both be bypassed. Finally, for IQ data, the signal is interpolated to the DAC sample rate.
As shown in Figure 127, the DFE subsystem also includes various signal conditioning algorithms, such as LO leakage (LOL) suppression
and quadrature error correction (QEC). Besides those, it also provides power amplifier protection and transmitter attenuation control
blocks.
The output of DFE will first go through the DAC in the AFE subsystem. The DAC standard clock rate can be programmed to be 184.32,
368.64, or 552.96 MHz, which is set by the profile. (Note other sample rates could also be supported when arbitrary sample rate is
employed.) Then, the DAC output is filtered by the LPF and input to the up-conversion mixer.
As shown in Figure 127, the ADRV9001 device also supports another method of FM/FSK modulation named Direct FM/FSK
modulation. In this mode, the DUC, IQ FM/FSK, the interpolation stage 2, power amplifier protection and transmitter attenuation blocks
(digital part) are all bypassed. RFPLL is used to generate a constant envelope phase-modulated signal by modulating the Sigma-Delta
Modulator (SDM) with the data stream. In Direct FM/FSK, both DAC and LPF can be powered down.
In the following subsections, major transmitter functionalities will be discussed.
DIGITAL FRONT END (DFE)
Programmable FIR Filter (PFIR)
The PFIR has 128 taps with 24-bit coefficients. There are 2 FIR filters, which are PFIR_I and PFIR_Q as shown in Figure 128. It can be
configured to operate in parallel, one for I data and one for Q data in digital IQ modulation applications such as LTE. It can also be
configured to use PFIR_I or PFIR_Q only or to operate both filters sequentially for FM/FSK applications. User could optionally use this
PFIR for their applications by loading a set of PFIR coefficients.
Before this PFIR, use can also optionally perform interpolation and the interpolation factor supported in the current release is 1 and 2. In
such a case, the PFIR can be designed to perform filtering after interpolation. The achieve unity gain, the PFIR coefficients scaling factor
can be calculated as 2^23*Interpolation_factor/(Sum of the filter coefficients). If fewer than 128 coefficients are specified by the user,
zeros will be appended.
Figure 128. Programmable FIR Filters
INTERNAL
OBSERVATION
DAC
Tx1/Tx2
Tx1+,
Tx2+
Tx1–,
Tx2–
DAC
90°
0°
INTERPOLATION
STAGE 2
INTERPOLATION
DFEAFE
INTERPOLATION
STAGE 1
PROGRAMMABLE
128 TAP FIR FILTER
NCO
SYMBOL
MAPPING/
INTERPOLATION
DATA
PORT
TX1/2_DCLK_OUT±
PA
PROTECTION
TX
ATTENUATION
FREQUENCY
DEVIATION MAPPER
FOR DIRECT
LO MODULATION
RF PLL
LOOPBACKLO
QUADRATURE
ERROR
CORRECTION
LO LEAKAGE
SUPPRESSION
DIGITAL
PRE-DISTORTION
I/Q
FM/FSK
DIGITAL
UPCONVERTER
LPF
LPF
2
TX1/2_QDATA_IN±
2
TX1/2_IDATA_IN±
2
TX1/2_STROBE_IN±
2
TX1/2_DCLK_IN±
2
24159-087
TO NARROWBAND
INTERPOLATOR
AFTER TX
PREPROCESSING
PFIR_Q
{I,Q}
PFIR_I
I
I,Q
Q
I
24159-088
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