Preliminary Technical Data UG-1828
Rev. PrB | Page 137 of 277
WB/NB DECIMATION
(DECIMATION
STAGE 2)
HB FILTERING
(DECIMATION
STAGE 1)
INTERFACE
GAIN
(SLICER)
LVDS/CMOS
API
API DGPIO(S)
RSSI
HB PEAK
DETECTOR
POWER
DETECTOR
ANALOG
PEAK
DETECTOR
GAIN CONTROL BLOCK
(AGC, MGC)
FRONT END
ATTENUATOR
MUX
DIGITAL
GAIN CONTROL
ADC
TIA
GAIN
EXTERNAL
GAIN
GAIN
24159-106
Figure 133. Rx Data Path and Gain Control Blocks
In this gain table, each row provides a unique combination of 6 fields including Front-end Attenuator, TIA Control, ADC Control,
External Gain Control, Phase Offset and Digital Gain/Attenuator. Among them, the TIA Control which sets the TIA gain, the ADC
Control which sets the ADC gain and the Phase Offset which compensates for the phase discontinuity during gain change are reserved
for future use.
Based on the row of this table selected, either by the user in MGC mode, or automatically by the device in AGC mode, the gain control
block updates the variable gain elements depicted by the dash lines. In the MGC mode, the user can control the gain control block using
the API commands and DGPIOs.
Table 53 shows the first three and last three rows in a sample gain table.
Table 53. Sample Rows from the Default Rx Gain Table
Gain Table
Index
Front-End Attenuator
Control Word [7:0]
TIA
Control
ADC
Control
External Gain
Control [1:0]
Phase
Offset
Digital Gain/Attenuator
Control Word
[10:0]
195 248 0 0 0 0 -2
196 247 0 0 0 0 -17
197 247 0 0 0 0 −7
… … … … … … …
253 28 0 0 0 0 −2
254 14 0 0 0 0 −1
The gain table index is the reference for each unique combination of gain settings in the programmable gain table. The current possible
range of the gain table is 195 to 255. The gain index region is user configurable. An API function
adi_adrv9001_Rx_MinMaxGainIndex_Set() could be called by the user right after loading the gain table to load multiple gain table
regions and switch between multiple gain table regions during runtime.
Note the External Gain Control which sets the external gain is not supported currently. It is used to control two AGPIO pins for each
receiver. Depending on the hardware register setting, the AGPIO pins for Receiver 1 and Receiver 2 can be selected from AGPIO[3:0],
AGPIO[7:4] and AGPIO[11:8]. Table 53 shows an example of Receiver 1 and Receiver 2 external gain element control when AGPIO[0:3]
is selected (Note it is also possible to use AGPIO[1:0] for Receiver 2 and AGPIO[3:2] for Receiver 1. Please refer to GPIO section in the
User Guide for more information.).
Table 54. An Example of Analog GPIOs for External Gain Element Control
Receiver AGPIO Pins to Control External Gain Element
Rx1 AGPIO[1:0]
Rx2 AGPIO[3:2]
These AGPIOs must be enabled as outputs and set for external gain functionality. The 2-bit value programmed is directly related to the
status of these AGPIO pins. For example: if the external gain word of the Receiver 1 gain table is programmed to 3 in selected gain
index, then AGPIO[0] and AGPIO[1] will be high if AGPIO[1:0] is used to control external gain element as the example show in Figure 131.
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