UG-1828 Preliminary Technical Data
Rev. PrC | Page 88 of 338
MULTICHIP SYNCHRONIZATION
INTRODUCTION
Multi-chip synchronization (MCS) is necessary when application requires deterministic latency between data paths, such as MIMO
applications, which will require multiple ADRV9001 devices. MCS is the solution for this problem to have the data in multiple channels
aligned in time. Certain applications not only require the delay to be deterministic but also require phase to be the same. ADRV9001 will
also support PLL phase synchronization as one of the operation modes.
THEORY OF OPERATION
Figure 81, illustrates the synchronization between multiple ADRV9001 devices using a shared input pin, MCS. The MCS signal is
generated by the external clock chip (for example, AD9528) using device clock DEV_CLK and captured by each ADRV900x device using
negative or positive edge of DEV_CLK to meet setup and hold time with good margins. Each ADRV900x device uses this sampled MCS
to synchronize all internally generated clocks which make them aligned between all devices internal clocks.
Figure 81 Multi-chip Synchronization System Diagram
Sampled MCS
MCS pulse signal will be sampled internally by ADRV9001 by the DEV_CLK signal rising or falling edge. Figure 82 shows the example
that MCS pulse being sampled by the rising edge of the DEV_CLK. This process guarantees that the sampled MCS signal, which is used
to synchronize all ADRV9001 devices are time aligned.
MCS
SAMPLING
CLK PLL
DEV_CLK MCS
MCS
SAMPLING
DIGITAL CLOCK MCS
DIGITAL CLOCK
RX LVDS CLOCK MCS
RX LVDS CLOCK
CLKGEN
DIVIDERS
MCS
SAMPLING
DIGITAL
MCS
SAMPLING
ANALOG
ADRV900x (2)
MCS
SAMPLING
CLK PLL
DEV_CLK
MCS_2
MCS_1
CLK_2
CLK_1
MCS
CLOCK GENERATION
CLOCK CHIP
MCS GENERATION
MCS
SAMPLING
DIGITAL CLOCK MCS
DIGITAL CLOCK
RX LVDS CLOCK MCS
RX LVDS CLOCK
CLKGEN
DIVIDERS
MCS
SAMPLING
DIGITAL
MCS
SAMPLING
ANALOG
ADRV900x (1)
24159-072
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