Analog Devices ADRV9002

Preliminary Technical Data UG-1828
Rev. PrB | Page 99 of 277
The user must then either pad their data with zeros or a known pattern and start transmitting as soon as the interface is enabled (first
timing diagram) or hold off from their transmission until t
propagationDelay prior to the analog front end being enabled (second timing
diagram).
24159-497
FRAMING ON AIR
USER STARTS
SENDING FIXED
PATTERNS/ZEROS
USER STARTS
SENDING
VALID DATA
FRAMING AT BBIC
PIN: HOP
PIN: Rx SETUP
Tx INTERFACE
Tx ANALOG POWER
Tx ON: ANTENNA SWITCH
FPGA Tx DMA
t
RxPD
t
TxEnaRise2AnaOn
t
TxEnaSetup
ZEROS/
PATTERN
VALID DATA
TRANSITION
DWELL
DWELL
NOT
ON
AIR
Figure 101. Tx Only with Short Propagation Delay, Padded Data Method
24159-498
FRAMING ON AIR
USER STARTS
SENDING FIXED
PATTERNS/ZEROS
USER STARTS
SENDING
VALID DATA
USER ENABLES
FPGA Tx DMA
FRAMING AT BBIC
PIN: HOP
PIN: Rx SETUP
Tx INTERFACE
Tx ANALOG POWER
Tx ON: ANTENNA SWITCH
FPGA Tx DMA
t
RxPD
t
TxEnaRise2AnaOn
t
TxEnaSetup
ZEROS/
PATTERN
VALID DATA
TRANSITION
DWELL
DWELL
NOT
ON
AIR
Figure 102. Tx Only with Short Propagation Delay, FPGA Delay