UG-1828 Preliminary Technical Data
Rev. PrC | Page 48 of 338
SPI BUS SIGNALS
The SPI bus consists of the following signals:
• SCLK
• CSB
• SDIO and SDO
SCLK
SCLK is the serial interface reference clock driven by the baseband processor (uses the SPI_CLK pin). It is only active while CSB is low.
The minimum SCLK frequency is 1 kHz. The maximum SCLK frequency is 50 MHz.
CSB
CSB is the active-low chip select that functions as the bus enable signal driven from the baseband processor to the device (uses the
SPI_EN pin). CSB is driven low before the first SCLK rising edge and is normally driven high again after the last SCLK falling edge. The
device ignores the clock and data signals while CSB is high. CSB also frames communication to and from the device and returns the SPI
interface to the ready state when it is driven high.
Forcing CSB high in the middle of a transaction aborts part or all of the transaction. If the transaction is aborted before the instruction is
complete or in the middle of the first data word, the transaction is aborted and the state machine returned to the ready state. Any
complete data byte transfers prior to CSB deserting are valid, but all subsequent transfers in a continuous SPI transaction are aborted.
SDIO and SDO
When configured as a 4-wire bus, the SPI uses two data signals: SDIO and SDO. SDIO is the data input line driven from the baseband
processor (uses the SPI_DIO pin) and SDO is the data output from the device to the baseband processor in this configuration (uses the
SPI_DO pin). When configured as a 3-wire bus, SDIO is used as a bidirectional data signal that both receives and transmits serial data.
The SDO port is disabled in this mode.
The data signals are launched on the falling edge of SCLK and sampled on the rising edge of SCLK by both the baseband processor and
the device. SDIO carries the control field from the baseband processor to the device during all transactions, and it carries the write data
fields during a write transaction. In a 3-wire SPI configuration, SDIO carries the returning read data fields from the device to the
baseband processor during a read transaction. In a 4-wire SPI configuration, SDO carries the returning data fields to the baseband
processor.
The SDO and SDIO pins transition to a high-impedance state when the CSB input is high. The device does not provide any weak pull-ups
or pull-downs on these pins. When SDO is inactive, it is floated in a high-impedance state. If a valid logic state on SDO is required at all
time, an external weak pull-up/down (10 kΩ value) should be added on the PCB.
SPI DATA TRANSFER PROTOCOL
The SPI is a flexible, synchronous serial communication bus allowing seamless interfacing to many industry standard microcontrollers
and microprocessors. The serial I/O is compatible with most synchronous transfer formats, including both the Motorola SPI and Intel
SSR protocols. The control field width for this device is limited to 16 bits, and multi-byte IO operation is allowed. This device cannot be
used to control other devices on the bus; it only operates as a slave.
There are two phases to a communication cycle. Phase 1 is the control cycle, which is the writing of a control word into the device. The
control word provides the serial port controller with information regarding the data field transfer cycle, which is Phase 2 of the
communication cycle. The Phase 1 control field defines whether the upcoming data transfer is read or write. It also defines the register
address being accessed.
Phase 1 Instruction Format
The 16-bit control field contains the following information:
MSB D14:D0
R/Wb—Bit 15 of the instruction word determines whether a read or write data transfer occurs after the instruction byte write. Logic high
indicates a read operation; logic zero indicates a write operation.
D14:D0—Bits A<14:0> specify the starting byte address for the data transfer during Phase 2 of the I/O operation.
All byte addresses, both starting and internally generated addresses, are assumed to be valid. That is, if an invalid address (undefined
register) is accessed, the IO operation continues as if the address space were valid. For write operations, the written bits are discarded, and
read operations result in logic zeros at the output.
To Next Page
Loading...
Need help?
General
