Analog Devices ADRV9002 User Manual

Preliminary Technical Data UG-1828
Rev. PrC | Page 179 of 338
D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2
D1
D0D20D21
D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2
D1
D0D20D21
D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2
D1
D0D20D21
Input Power Level 1
Input Power Level 2
Input Power Level 3
Figure 163. Bit Width of Input Signal with Increasing Power Levels
The slicer is used to attenuate the data such that it can fit into the resolution of the data port. Since the output is a shifted version of the
input, the slicer can only handle gains that are in ±6 dB steps.
Figure 164 explains the slicer operation. For Power Level 1, the slicer shift value is calculated as 0 so the 16-bit output data is taken from
D15 – D0. As the power level increases, the bit-width of the signal has increased. For Power Level 2, now the bit-width is 17. The slicer
shift value becomes 1 so the 16-bit output data is taken from D16 – D1. This is equivalent to apply 6 dB of attenuation by slicer which
ensures that the bit-width of the signal is 16 once more; that is, the 16 MSBs have been selected (sliced) with the LSB dropped. When the
power level further increases as Power Level 2, the signal bit-width becomes 18-bit. The slicer shift value becomes 2 so the 16-bit output
data is taken from D17 – D2, which is equivalent to apply 12 dB of attenuation by slicer or slice the 16 MSBs dropping the 2 LSBs.
D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D20D21
D19 D18 D17 D16 D15
D14
D13 D12 D11 D10 D9 D8 D7 D6
D5
D4 D3 D2 D1 D0D20D21
D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D20D21
Slicer Shift Value
0
1
2
Input Power Level 1
Input Power Level 2
Input Power Level 3
Figure 164. Slicer Bit Selection with Different Input Power Levels
The slicer algorithm assumes a max PAR of 15dB and it adjusts the interface gain such that the measured signal power + 15 dB is less than
0 dBFS. For NB applications, the interface gain is from −36 dB to +18 dB and for WB applications, the interface gain is from −36 dB to
0 dB in 6 dB step size.
Similarly, the baseband processor could retrieve the interface gain through API commands to scale the power of the received signal to
determine the power at the input to the device (or at the input to an external gain element if considered part of the digital gain
compensation).
Mode 4: Digital Gain Compensation with External Interface Gain Control
This mode is similar to mode 3 except that user controls interface gain by selecting a proper value. The baseband processor could measure
the input signal power or use the power measurement done by RSSI in the device to determine the interface gain. Then through API commands
and the Slicer will operate in the same way as mentioned in mode 3. For NB applications, the interface gain is from −36 dB to +18 dB and for WB
applications, the interface gain is from −36 dB to 0 dB in 6 dB step size. This mode could be used especially when baseband processor
input signal clipping is observed by the user.
DIGITAL GAIN CONTROL AND INTERFACE GAIN API PROGRAMMING
The API function adi_adrv9001_Rx_InterfaceGain_Configure() is provided to configure the interface gain. The configuration structure
adrv9001_RxInterfaceGainCtrl_t is defined as the following:
typedef struct adi_adrv9001_RxInterfaceGainCtrl
{
adi_adrv9001_RxInterfaceGainUpdateTiming_e updateInstance; /* Time at which Rx interface
gain control must be updated. 0: To be updated at start of next frame 1: To be updated
immediately */
adi_adrv9001_RxInterfaceGainCtrlMode_e controlMode; /* 0: Uses internal Rx interface gain
value 1: Uses external Rx interface gain value. Gain value must be provided in this case. */

Analog Devices ADRV9002 Specifications

General

Brand	Analog Devices
Model	ADRV9002
Category	Transceiver
Language	English