UG-1828 Preliminary Technical Data
Rev. PrC | Page 178 of 338
gain is not required. In the second mode, it passes the full 22-bit I/Q data from the receiver data path to the interface without rounding.
Therefore, it lowers the quantization noise without the need for additional interface gain. It uses 32 bit I data and 32 bit Q data on the
interface for CMOS 1-lane (64-bit) and LVDS 2-lane (32-bit I data and 32-bit Q data). Besides including the 22-bit I/Q data, the 32-bit
data also includes some extra fields, which are 1 bit of slicer gain or AGC gain change indicator and one of the followings: zeros, interface
gain or AGC gain index. Please refer to Data Interface section for more details.
Figure 162 is a block diagram of the digital gain control portion of the Rx chain, showing the locations of the various blocks in the
simplified datapath.
Figure 162. Gain Control and Slicer Section of the Receiver Datapath
It can be seen from Figure 162that digital gain control is performed in the WB/NB Decimation block. In NB and WB applications, the
digital gain control is actually performed at different stages of the receiver data chain to achieve optimal performance, which is simplified
in Figure 162. The slicer must be dependent on the desired signal power alone and must be done only when all the interfering signals
have been filtered out, for example, close to the end of the datapath. The Slicer operation can either be controlled automatically by the
device internally or by user externally through API commands. When controlled internally the RSSI block is used to determine the
amount of interface gain.
The following sections describe four different digital gain control modes in the device.
Mode 1: No Digital Gain Compensation with Internal Interface Gain Control
In this mode the digital gain block is used for gain correction. It applies a small amount of digital gain/attenuation to provide consistent gain steps
in a gain table. The premise is that because the analog attenuator does not have consistent steps in dB across its range then the digital gain block
can be used to even out the steps for consistency (the default table uses the digital gain block to provide consistent 0.5 dB steps).
With internal control, the device automatically applies the interface gain determined by RSSI, which measures the input signal power
right before the slicer. Note in the gain correction mode, interface gain less than 0 is not needed since the Rx output level should not
exceed 0 dBFS through either AGC or MGC. When in NB applications, the interface gain range could be from 0 dB to 18 dB in 6 dB step
size (0, 6, 12, 18) for improving the sensitivity when a quantizer is used. In WB applications, as discussed earlier, the sensitivity is already
satisfied by the high sampling rate so the interface gain is always 0.
After applying the interface gain, the signal is provided to the data port. The baseband processor could retrieve the interface gain through
API commands to scale the power of the received signal to determine the power at the input to the device (or at the input to an external
gain element if considered part of the digital gain compensation).
Mode 2: No Digital Gain Compensation with External Interface Gain Control
This mode is similar to mode 1 except that user controls the interface gain manually. Similarly, when in NB applications, the interface
gain range could be selected from 0 dB to 18 dB in 6 dB step size when a quantizer is used while in WB applications the interface gain is
fixed at 0 dB.
Mode 3: Digital Gain Compensation with Internal Interface Gain Control
In this mode gain compensation is used and the interface gain is determined internally. The device should be loaded with gain tables that
compensate for the analog front-end attenuation applied. Thus, as the analog front-end attenuation is increased, and equal amount of
digital gain is applied. The interface gain is determined by RSSI. If the power level is too high, the Slicer will shift the signal properly
before sending to the data port to avoid saturation.
Slicer example: Considering 3 different input signal power levels. The Power Level 1 fits a data length of 16 bit-width. The Power Level 2
is 0 dB to 6 dB higher than Power Level 1which increases the bit-width by 1. The Power Level 3 is 6 dB to 12 dB higher than Power Level 1
which further increases bit-width by 1. Figure 163 outlines this effect, with gray boxes indicating the valid (used) bits in each case.
WB/NB
DECIMATION
INTERFACE
GAIN
(SLICER)
LVDS/CMOS
MUX
API
RSSI
SIGNAL AFTER
HB FILTERING
DIGITAL
GAIN CONTROL
24159-120
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