UG-1828 Preliminary Technical Data
Rev. PrC | Page 134 of 338
characteristics are automatically tuned internally to achieve optimal performance for different applications. In principle, the AFE design is
based on WB architecture with a very high dynamic range to absorb both desired signal and interference without distortion. Therefore, in
such a design, very little channelization or blocker filtering is needed through LPF since the HP and LP ADC can simultaneously absorb
weak signals and large blockers. Blocker suppression and channelization are then achieved efficiently in the digital signal path. After
ADC, the digital output signal will be further processed through multiple stages in DFE.
Figure 137. Rx Signal Chain Block Diagram
The ADRV9001 supports 3 standard ADC clocks, which are ADC-H clock 2211.84MHz, ADC-M clock 1474.56MHz and ADC-L clock
1105.92MHz for both HP ADC and LP ADC (Note ADC clock could vary with arbitrary sample rate.). In the DFE subsystem, the ADC
output signal at 3 different sample rates will go through 2 decimation stages as shown in Figure 128 to convert to the desired sample rate
by using a flexible combination of decimators. Between the 2 decimation stages, there is an optional DDC which is employed in the
applications which adopts IF reception scheme.
At different decimation stages, several signal conditioning algorithms are performed, which are overload detection for gain control, DC
offset correction (DC) and quadrature error correction (QEC) as shown in Figure 137. The overload detection result is used by automatic
gain control (AGC) or manual gain control (MGC) algorithms to properly control both analog and digital gain through a receiver gain
table. The analog gain is applied at the front end attenuator to avoid overload/underload situations. The digital gain is applied at the gain
compensation block in the receiver datapath and it has 2 major functionalities: one is to correct the small step size inaccuracy of the front
end analog gain and the other is to compensate for the front end gain change completely so that it is transparent to users. Different
receiver gain tables are loaded for either correction or compensation based on user’s configuration during the device initialization. In
ADRV9001, a sophisticated gain control mechanism (AGC/MGC) is provided, see the Rx Gain Control section for more details. DC and
QEC are used to correct the DC offset and quadrature error so that the signal distortion could be minimized to achieve an optimal
performance before sending data to baseband processor. To achieve best performance for different applications, QEC algorithm is
designed differently for WB and NB applications.
After decimation stage 2, the ADRV9001 provides an option to correct small carrier frequency offset through API commands, followed
by a 128-tap programmable PFIR as a channel selection filter. In the future, API commands will be provided for PFIR for more user
interactions.
After PFIR, besides applying the digital gain as discussed earlier, an interface gain could be optionally applied by utilizing the signal
strength measurement from RSSI. The interface gain is applied through a “Slicer” by properly shifting the signal. When the signal is large,
it could be used to avoid saturate the data port due to a limited bit-width, and when the signal is small, it could be used to avoid lose
sensitivity. An API command is provided to the user to read the signal strength measurement. The interface gain can be applied
automatically in the device or manually by the user through API commands. This is beneficial when saturation is observed in baseband
processor. See the Rx Gain Control section for more details.
The RSSI could also be used as the signal detector in Rx Monitor Mode. In NB applications, at the end of the datapath, the device
provides an optional capability to discriminate the FSK frequency shift and in addition, detect the DMR sync patterns, which is critical for
receiver Monitor Mode. Note phase offset correction capability is also provided at the end of the receiver datapath to ensure the signal
fidelity. In the future, API command will be provided to allow user interaction. Finally, the output signal is sent through CMOS-
SSI/LVDS-SSI data port to baseband processor for further processing.
ANALOG FRONT-END COMPONENTS
Analog Front Attenuator
The analog front attenuator is a PI resistive network that in conjunction with the passive mixer provides a constant 100 Ohm differential
input impedance. It is controlled by the gain control functionality in the receive datapath to adjust the signal gain to avoid overload the
datapath through overload detectors. When a strong interferer presents, the gain will be decreased and when the interferer disappears, the
gain will be increased so that the desired signal level could be adjusted back to the proper level.
The attenuator has 256 gain settings providing an receiver attenuation range from 0 to 20*log(1/256) = -48dB. Typically, only a subset of
this range will be used. In ADRV9001, the current range of the attenuation is from 0 to -30dB with a 0.5dB resolution. The gain of the
attenuator is calculated by the following equation:
HP ADC
RX1A+,
RX2A+
RX1A–,
RX2A–
RX1B+,
RX2B+
RX1B–,
RX2B–
Rx1
LP ADC
LP ADC
HP ADC
INTERNAL
OBSERVATION
LO LOOPBACK
LPF
LPF
90°
0°
DECIMATION
STAGE 1
OVERLOAD
DETECTORS
MANUAL AND
AUTOMATIC
GAIN CONTROL
DC OFFSET
CORRECTION
QUADRATURE
ERROR
CORRECTION
DECIMATION
AFE DFE
DECIMATION
STAGE 2
FREQUENCY
OFFSET
CORRECTION
PROGRAMMABLE
CHANNEL FILTER
(128 TAP FIR)
GAIN
COMPENSATION
PHASE
OFFSET
CORRECTION
DATA
PORT
INTERFACE
GAIN
RECEIVER SIGNAL
STRENGTH
INDICATOR
NARROW
BAND FSK
DISCRIMINATION
DMR SYNC
DETECTION
DIGITAL
DOWN
CONVERTER
RX1/2_QDATA_OUT±
2
RX1/2_IDATA_OUT±
2
RX1/2_STROBE_OUT±
2
RX1/2_DCLK_OUT±
2
24159-097
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