Preliminary Technical Data UG-1828
Rev. PrC | Page 17 of 338
Table 4. Constrains and Limitations in 1T1R FDD with DPD Type Application
Functionality Constrains and Limitations
In 1T1R FDD+DPD type applications, ADRV9001 can use its internal LO to generate RF LO1 for uplink and RF LO2 for
downlink. For applications with stringent RF LO requirements, the user can use external LO inputs. External LO1
operating at 2× RF LO can be used for uplink and separate external LO2 operating at 2× RF LO for downlink.
RF Front End For LO generation, the ADRV9001 uses internal VCO that generates square wave type signal. A square wave LO would
produce harmonics. For example: depending of RF matching used on the RF ports user 2nd LO harmonic can be as
high as −50 dBc and 3rd harmonic can be as high as −9 dBc. Therefore, the RF filtering on the Rx and Tx path must
ensure that signals at the LO harmonic frequencies (up to 9th in some cases) are not affecting overall system
performance.
DPD The DPD functionality can be used in the 1T1R FDD mode with second Tx being disabled. Maximum channel
bandwidth that DPD can support is limited by ADRV9001 RF bandwidth divided by 3 or by 5. The DPD operation can
be performed by ADRV9001 or Rx data can be sent to baseband processor via Rx data port serving as observation Rx.
Rx path used during DPD operation to perform Tx observation is also used by the Tx tracking calibrations. In case of
external DPD, user must ensure that access to the Rx path during Tx slots is time-shared between external DPD
operation and internal Tx calibrations.
Calibrations During Rx initialization sequence, the user needs to ensure that there are no signals present at the Rx input (external
LNA should be disabled) and appropriate termination should be present at LNA output to avoid reflections of Rx
calibration tones that are present at Rx input. The maximum input signal amplitude must not exceed −82 dBm/MHz
for wideband modes, TBD dBm/MHz for narrowband modes.
During Tx initialization sequence, user needs to ensure that Power Amplifier is power down to avoid unwanted
emission of Tx calibration tones at the antenna. ADRV9001 needs to access Rx datapath during Tx time slots for Tx
tracking calibration to operate. If user use Tx observation path with DPD functionality performed by baseband
processor, then access to the Rx datapath during Tx slots must be time-shared between DPD operation and Tx
calibrations.
AGPIOs Analog GPIOs (operating at 1.8 V level) can be used as read or write digital levels of in the end user system. AGPIOs
can be used to control states of external components (for example, RF Switch, LNA) or read back digital logic levels
from external components.
DGPIOs Digital GPIOs can be used to perform real-time monitoring of states of internal ADRV9001 blocks. Digital GPIOs
operating as inputs can allow user to control Rx gain, Tx attenuation, AGC operation and other elements of ADRV9001
TRx. Depending on the ADRV9001 operation up to 4 GPIOs may be used by data port interface.
AuxADC AuxADC can be used to monitor analog voltage (for example, temperature sensor). Maximum AuxADC input voltage
must not exceed 0.9 V.
AuxDAC AuxDAC can be used to control the VCXO responsible for generating the ADRV9001 device clock, generate pre-
configured ramp up/down signal that can be used to control power amplifier bias or control any circuitry that requires
analog control voltage up to 1.8 V.
DEV_CLK_OUT ADRV9001 provides divided down version of DEV_CLK reference clock input signal on the DEV_CLK_OUT output. This
output is intended to provide a reference clock signal to the digital components in the overall system. This output can
be configured to be active after power up and before ADRV9001 configuration stage.
Multichip Sync If there is no need for multichip synchronization, the ADRV9001 can be initialized using API functions only.
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