Analog Devices ADRV9002

UG-1828 Preliminary Technical Data
Rev. PrB | Page 172 of 277
1
Based on 38.4M device clock.
• Power down mode 0 is the default power saving if power saving API is not called to set other values. In this mode, TX/RX enable pin
will automatically trigger powering up/down the TX/RX analog and digital datapath components such as Mixer, A/D, filters, and so
on The transition time is very short around TBD us.
• Power down mode 1 would power down internal RF PLLs in addition to mode 0 power down. After powering up, PLL requires
parameters restoration (TBD) or re-calibration, so it takes more time to power up.
• Power down mode 2 would power down some LDOs related to channels and RF PLLs in addition to mode 1 power down.
• Power down mode 3 powers down the TX/RX channels and PLLs (clock PLL, RF PLLs) only. No LDOs are powered down.
• Power down mode 4 powers down Clock PLL and system LDOs related to TX/RX channels in addition to mode 3 power down.
• Power down mode 5 powers down almost the whole ADRV9001 chip including ARM and memory except some wake up circuits.
POWER-DOWN/POWER-UP CHANNEL IN CALIBRATED STATE
User could power down/up individual channel (TX1/TX2/RX1/RX2) dynamically in Calibrated State if these channels are statically
enabled in device profile. adi_adrv9001_Radio_Channel_PowerDown() can be called to power down the specified channel, it will power
down the channel related LDOs and PLL for the channel in, in addition to datapath power down.
adi_adrv9001_Radio_Channel_PowerUp() is used for power up the specified channel. User should notice that these two APIs can only
be called in Calibrated state.
Figure 161 shows a DMR radio switch from TX only frames into TX/RX alternate frames, ADRV9001 is initialized with Tx and Rx
enabled, at the beginning of TX only frames, baseband processor can bring the RX channel into Calibrated State and power it down.
Then before the transition of TX/RX alternate frames, baseband processor can power up RX and move RX into Primed state. The power
saving of TX channel in the green area would be addressed by power down modes in the following sections.
RX ON
(15ms)
TX ON
(30ms)
SLEEP
(30ms)
SLEEP
(30ms)
TX ON
(30ms)
TX ON
(30ms)
TX ON
(30ms)
ACTIVE TX STATE
TRX
ACTIVE TX
REVERSE
STATE
24159-135
Figure 162. DMR Typical State Transition
Another use case example, if 4 channels ((TX1/TX2/RX1/RX2) are enabled in the profile, user can power down the channels not used
temporarily after moving those channels to Calibrated state.
DYNAMIC INTERFRAME POWER SAVING
Dynamic inter-frame power saving is running automatically during all regular TDD TX/RX operations, higher level power down mode
can be configured to get more power saving if the application has longer TX/RX transition time. DGPIO pins could be configured to
support additional power savings.
There are two power saving choices that can be applied for various TDD interframe scenarios, one is Channel Power Saving and another
one is System Power Saving, users can configure either or both of these two options according to their system specification.
Channel Power Saving (CPS)
Channel power saving is to save power on channel granularity for dynamic TDD inter-frame operations. There are two kinds of power
saving events triggered by either TX/RX Enable pins or DGPIO pins respectively. The configuration selects power saving modes for both
kinds of events. Only power down mode 0-2 can be configured for CPS.
TX_ENABLE/RX_ENABLE Pin Triggers Power Saving
Power saving triggered by TX_ENABLE/RX_ENABLE pin powers up/down based on TX_ENABLE/RX_ENABLE rising or falling edges.
TX_ENABLE/RX_ENABLE rising edge powers up the components based on power down mode and falling edge powers down them.
Figure 162 shows TX/RX Enable pin powers up/down channels. If Tx/Rx Enable Pin power down mode is set to mode 1, TX1/RX1
Enable falling edge powers down TX1/RX1 PLL and TX1/RX1 datapath, rising edge powers them up. As mentioned previously, the
higher power down mode, the longer recovery time, users should make sure their system has enough transition time between the power
down and power up of the same component if users set a high power down mode. For example: in Figure 162, if TX1 and RX1 uses the
same internal PLL and there is very short transition time between TX enable falling edge and RX enable rising edge, then mode 1 and 2
should not be selected because the same PLL and LDOs are always used.