Preliminary Technical Data UG-1828
Rev. PrB | Page 223 of 277
Table 100. Impedance Table
Layer
Structure
Type
Coated
Microstrip
1
Target
Impedance
(Ω)
Impedance
Tolerance
(Ω)
Target
Linewidth
(mils)
Edge
Coupled
Pitch
(mils)
Reference
Layers
Modelled
Linewidth
(mils)
Modelled
Impedance
(Ω)
Coplaner
Space
(mils)
1 Single
ended
N/A 50.00 ±5 12.00 0.00 (2) 13.00 50.87 9.50
1 Single
ended
Yes 50.00 ±5 13.50 0.00 (2) 12.00 50.42 10.75
1 Edge
Coupled
Differential
Yes 100.00 ±10 8.25 15.25 (2) 8.00 100.43 9.15
1 Edge
Coupled
Differential
N/A 100.00 ±10 7.50 14.50 (2) 9.00 100.55 9.25
3 Single
ended
N/A 50.00 ±5 4.00 0.00 (2, 4) 4.25 49.53 17.88
3 Edge
Coupled
Differential
N/A 100.00 ±10 3.75 10.75 (2, 4) 3.75 100.86 12.02
7 Edge
Coupled
Differential
N/A 100.00 ±10 6.00 14.25 (6, 8) 6.00 99.75 12.02
9 Edge
Coupled
Differential
N/A 100.00 ±10 6.25 15.00 (8, 11) 6.00 100.68 12.14
10 Edge
Coupled
Differential
N/A 100.00 ±10 4.25 9.50 (11, 8) 4.50 100.23 11.89
12 Edge
Coupled
Differential
Yes 100.00 ±10 8.00 15.25 (11) 8.00 100.80 10.00
12 Single
ended
Yes 50.00 ±5 12.00 0.00 (11) 12.00 50.31 10.00
12 Edge
Coupled
Differential
N/A 100.00 ±10 7.50 14.50 (11) 9.00 100.55 9.25
12 Edge
Coupled
Differential
N/A 100.00 ±10 8.25 15.50 (11) 8.25 99.64 10.02
1
N/A means not applicable.
FAN-OUT AND TRACE SPACE GUIDELINES
The ADRV9001 device family uses a 196-pin BGA 12 × 12 mm package. The pitch between the pins is 0.8 mm. This small pitch makes it
impractical to route all signals on a single layer. RF pins have been placed on the outer edges of the ADRV9001 package. This helps in
routing the critical signals without a fan-out via. Each digital signal is routed from the BGA pad using a 4.5 mil trace. The trace is
connected to the BGA using via-in-the-pad structure. The signals are buried in the inner layers of the board for routing to other parts of
the system.
Extra care must be taken to ensure that DEV_CLK signal is shielded from any potential source of noise. Recommended approach is to
use differential signaling for DEV_CLK clock. The data port interface signals when used in LVDS-SSI mode must be routed as 100 Ω
differential pairs. Figure 218 shows the fan out scheme of the ADRV9001 evaluation card. There are no traces being routed between BGA
pads on the top layer. As mentioned before ADRV9001 evaluation card uses via-in-the-pad technique. This routing approach can be
used for ADRV9001 if there are no issues with manufacturing capabilities.
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