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ADRV9002
Analog Devices ADRV9002 User Manual
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UG-1828
Preliminary Techn
ical Data
Rev.
PrC
| P
age
338
of
338
337
Table of Contents
Table of Contents
2
How to Use this Document
5
Block Diagram
6
Product Highlights
7
Adrv9002
7
Bandwidth and Sample Rate Support
7
Adrv9003
9
Adrv9004
9
ADRV9001 Example Use Cases
10
ADRV9001 in a Single-Band 2RT2R FDD Type Small-Cell Application
10
ADRV9001 in Dual-Band 2RT2R FDD Type Small-Cell Application
12
ADRV9001 in Single-Band 2T2R TDD Type Small-Cell Application
14
ADRV9001 in 1T1R FDD with DPD Type Application
16
ADRV9001 in TETRA Type Portable Radio Application
18
ADRV9001 in DMR Type Portable Radio Application
20
ADRV9001 in FDD Type Repeater Application
22
ADRV9001 in a FDD Type Repeater Application Using Internal Loopbacks
24
ADRV9001 in TDD Type Repeater Application
26
ADRV9001 in Radar Type Application
28
Software System Architecture Description
30
Software Architecture
30
Folder Structure
31
Customising the System Architecture and File Structure
32
Software Integration
35
Hardware Abstraction Layer
35
Developing the Application
41
System Initialization and Shutdown
43
TES Configuration and Initialization
43
API Initialization Sequence
44
Shutdown Sequence
46
Serial Peripheral Interface (SPI)
47
SPI Configuration
47
SPI Bus Signals
48
SPI Data Transfer Protocol
48
Timing Diagrams
50
SPI Test
51
Data Interface
52
General Description
52
Electrical Specification
52
CMOS Synchronous Serial Interface (CMOS-SSI)
54
LVDS Synchronous Serial Interface (LVDS-SSI)
61
Enhanced Rx SSI Mode
64
Power Saving for LSSI
65
SSI Timing Parameters
65
API Programming
65
CSSI/LSSI Testability and Debug
68
Microprocessor and System Control
70
System Control
71
Timing Parameters Control
71
Clock Generation
86
Multichip Synchronization
88
Introduction
88
Theory of Operation
88
MCS Substates (Internal MCS State Transition)
91
Procedure
91
Sample Delay and Read Delay
92
Phase Synchronization
94
Synthesizer Configuration and lo Operation
96
Clock Synthesizer
96
RF Synthesizer
96
Auxiliary Synthesizer
97
External lo
97
API Operation
99
Frequency Hopping
102
Key Signals
102
Modes of Operation
105
Channel and Profile Selection
106
Frequency Hopping Operation Ranges
107
Frequency Hopping Table
107
Frequency Hopping Calibrations
111
Frequency Hopping Timing
113
Additional Frequency Hopping Operations
117
Diversity Mode
121
Frequency Hopping with Rx/Orx Gain Control
121
Integration with Other Advanced Features
122
Transmitter Signal Chain
123
Data Interface
123
Datapath
124
Digital Front End (DFE)
124
Analog Front End (AFE)
129
Transmit Data Chain API Programming
130
Receiver/Observation Receiver Signal Chain
131
Receive Data Chain
133
Analog Front-End Components
134
Lpf
135
Adc
135
Digital Front End Components
136
DC Offset
136
Qec
137
DDC
137
Frequency Offset Correction
137
Pfir
137
Rssi
137
Receive Data Chain API Programming
138
Transmitter/Receiver/Observation Receiver Signal Chain Calibrations
140
Initial Calibrations
140
Tracking Calibrations
150
Receiver Gain Control
154
Receiver Datapath
155
Gain Control Modes
158
Gain Control Detectors
166
AGC Clock and Gain Block Timing
169
Analog Gain Control API Programming
170
Digital Gain Control and Interface Gain (Slicer)
177
Digital Gain Control and Interface Gain API Programming
179
Usage Recommendations
180
TES Configuration and Debug Information
181
Rx Demodulator
184
Rx Narrow-Band Demodulator Subsystem
184
Normal IQ Output Mode
188
Frequency Deviation Output Mode
188
API Programming
189
Power Saving and Monitor Mode
191
Power-Down Modes
191
Power-Down/Power-Up Channel in Calibrated State
192
Dynamic Interframe Power Saving
192
Monitor Mode
194
Digital Predistortion
197
Background
197
ADRV9001 DPD Function
197
ADRV9001 DPD Supported Waveforms
199
DPD with Frequency Hopping (FH)
199
ADRV9001 DPD Performance
199
Closed Loop Gain Control (CLGC)
201
DPD/CLGC Configuration
201
Board Configuration
210
Save and Load DPD Coefficients from Last Transmission
211
Define the Frequency Region When Performing DPD with FH
211
DPD/CLGC API Programming
212
DPD Tuning and Testing
212
CLGC Target Gain Measurment
215
Dynamic Profile Switching
216
Overview
216
Initial Calibration with DPS
216
Perform DPS on the Fly
217
DPS API Programming
218
Summary of DPS Limitations
218
DPS Operations in TES
219
General-Purpose Input/Output and Interrupt Configuration
221
Digital GPIO Operation
222
Analog GPIO Operation
225
Interrupt
226
Auxiliary Converters and Temperature Sensor
227
Auxiliary DAC (Auxdac)
227
Auxiliary ADC (Auxadc)
227
Temperature Sensor
228
RF Port Interface Information
229
Transmit Ports: TX1± and TX2
229
Receive Ports: RX1A±, RX1B±, RX2A±, and RX2B
229
External lo Ports: LO1± and LO2
229
Device Clock Port: DEV_CLK1
229
RF Rx/Tx Ports Impedance Data
229
General Receiver Port Interface
232
General Transmitter Bias and Port Interface
234
Impedance Matching Network Examples
236
Receiver RF Port Impedance Matching Network
236
Receiver RF Port Impedance Match Measurement Data
239
Transmitter RF Port Impedance Matching Network
241
Transmitter RF Port Impedance Match Measurement Data
242
External lo Port Impedance Matching Network
243
External lo Impedance Match Measurement Data
246
Connection for External Device Clock (DEV_CLK_IN)
247
DEV_CLK_IN Phase Noise Requirements
249
Connection for Multichip Synchronization (MCS) Input
250
Printed Circuit Board Layout Recommendations
251
PCB Material and Stack up Selection
251
Fan-Out and Trace Space Guidelines
252
Component Placement and Routing Priorities
253
RF and Data Port Transmission Line Layout
259
Isolation Techniques Used on the ADRV9001 Evaluation Card
266
Power Supply Recommendations
269
Power Management Considerations
269
Power Supply Sequence
269
Power Supply Domain Connections
270
Power Supply Architecture
272
RF and Clock Synthesizer Supplies
275
Power Supply Configurations
276
Summary
282
LDO Configurations
283
ADRV9001 Evaluation System
290
Initial Setup
290
Hardware Kit
290
Hardware Operation
295
Transceiver Evaluation Software (TES)
296
Automated Time Division Duplexing (TDD)
317
Tracking Calibrations
320
Digital Predistortion
321
TDD Enablement Delays
321
Auxiliary DAC/ADC
321
Frequency Hopping TES Examples
322
Radio State
331
Power/Temperature Monitoring
331
Driver Debugger
332
Log File
333
Automatically Generate Initialisation Code
334
Evaluation System Troubleshooting
334
4
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Analog Devices ADRV9002 Specifications
General
Brand
Analog Devices
Model
ADRV9002
Category
Transceiver
Language
English
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