Section 5 Status Messages
5-4
The IEEE488.1 status byte is used in the status model. This status byte is composed of
seven summary message bits given from the status data structure. To create the sum-
mary message bits, there are two models for the data structure: the register model and
the queue model.
The register model consists of the two registers used for recording
events and conditions encountered by a device. These two registers
are the Event Status Register and Event Status Enable Register. When
the result of the AND operation of both register contents is not 0, the
corresponding bit of the status bit becomes 1. In other cases, it
becomes 0. And, when the result of their Logical OR is 1, the
summary message bit also becomes 1. If the logical OR result is 0,
the summary message bit also becomes 0.
The queue in the queue model
is for sequentially recording the
waiting status values and data.
The queue structure is such that
the relevant bit is set to 1 when
there is data in it and 0 when it
is empty.
Register model
Queue model
In IEEE488.2, there are three standard models for status data structure, two register
models and one queue model, based on the register model and queue model explained
above. They are:
[1] Standard Event Status Register and Standard Event Status Enable Register
[2] Status Byte Register and Service Request Enable Register
[3] Output Queue
The Standard Event Status Register
has the structure of the previously
described register model. In this regis-
ter, bits are set for eight types of stand-
ard events encountered by a device.
[1] Power on, [2] User request,
[3] Command error, [4] Execution
error, [5] Device-dependent error,
[6] Query error, [7] Request for bus
control and [8] Operation complete.
The logical OR output bit is represent-
ed by Status Byte Register bit 5
(DIO6) as a summary message for the
Event Status Bit (ESB).
The Status Byte Register is a regis-
ter in which the RQS bit and the
seven summary message bits from
the status data structure can be set.
It is used together with the Service
Request Enable Register. When
the result of the OR operation of
both register contents is not 0,
SRQ goes ON. To indicate this,
bit 6 of the Status Byte Register
(DIO7) is reserved by the system
as the RQS bit, which indicates a
service request for the external con-
troller. The mechanism of SRQ
conforms to the IEEE488.1 stand-
ard.
The Output Queue has
the structure of the
queue model mentioned
above. Status Byte Reg-
ister bit 4 (DIO5) is set
as a summary message
for Message Available
(MAV) to indicate that
there is data in the out-
put buffer.
Standard Event Status Register
Status Byte Register Output Queue
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