Anritsu MT8801C - Bit Definition of Standard Event Status Register; Standard Event Status Register

Section 5 Status Messages
5-10
5.4 Standard Event Status Register
5.4.1 Bit definition of standard event status register
The standard event status register must be available on all devices conforming to the
IEEE488.2 standard. The diagram below shows the operation of the standard event
status register model. Because the operation of the model is the same as that for the
other models already described, the following only explains the meaning of each bit in
the standard event status register as defined in the IEEE488.2 standard.
disabled = 0, enabled = 128(2
7
)
disabled = 0, enabled = 64 (2
6
)
disabled = 0, enabled = 32 (2
5
)
disabled = 0, enabled = 16 (2
4
)
disabled = 0, enabled = 8 (2
3
)
disabled = 0, enabled = 4 (2
2
)
disabled = 0, enabled = 2 (2
1
)
disabled = 0, enabled = 2 (2
0
)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
&
&
&
&
&
&
&
&
Logical OR
Standard Event Status
Enable Register
Set by ∗ESE <n>
Read by ∗ESE?
Read by ∗ESR?
Power on (PON)
User request (URQ) --- not used
Command error (CME)
Execution error (EXE)
Device-dependent error (DDE)
Query error (QYE)
Request for bus control (RQC) --- not used
Operation complete (OPC)
Standard Event Status Register
ESB summary message bit
(To status-byte-register bit 5)