Anritsu MT8801C - Wait for Service Request after *OPC Is Sent

Section 5 Status Messages
5-20
5.6.3 Wait for service request after *OPC is sent
The MT8801C sets the operation-complete bit (bit 0) to 1 when executing the *OPC
command. The controller is synchronized with the MT8801C by waiting for SRQ
when the operation-complete bit is set for SRQ.
MSS 6 RQS
Status Byte Register
....... Output Queue
1
7
6
5
4
3
2
1
0
&
&
&
&
&
&
&
Logical OR
Standard Event Status
Register (ESR)
Power on
(Not used)
Command error
Execution error
Device-dependent error
Query error
(Not used)
Operation complete
&
Standard Event Status
Enable Register (ESE)
enabled = 2
0
7
5 ESB
4 MAV
3
2
1
0
MSS 6 RQS
• <Controller program>
[1] Enables the 20 bit (1) of the Standard Event Status Enable Register
[2] Enables the 25 bit (32) of the Service Request Enable Register
[3] Makes the device execute the specified operation
[4] Sends the ∗OPC command
[5] Wait for an SRQ interrupt (ESB summary message)
....Value of status byte: 2
6
+ 2
5
= 96
PRINT @1;"*ESE 1"
PRINT @1;"*SRE 32"
PRINT @1;"*OPC"
7
6
5
4
3
2
1
0